blob: 7a312602a09c5ed02e3bdf49a6c2e1d329c8431a [file] [log] [blame]
Simon Glassd188b182014-11-12 22:42:11 -07001/*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2008,2009
4 * Graeme Russ, <graeme.russ@gmail.com>
5 *
6 * (C) Copyright 2002
7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12#include <common.h>
Simon Glassa219dae2015-03-05 12:25:31 -070013#include <dm.h>
Simon Glass7430f102014-11-12 22:42:12 -070014#include <errno.h>
15#include <malloc.h>
Simon Glassd188b182014-11-12 22:42:11 -070016#include <pci.h>
Simon Glassa219dae2015-03-05 12:25:31 -070017#include <asm/io.h>
Simon Glassd188b182014-11-12 22:42:11 -070018#include <asm/pci.h>
19
Bin Meng4722c032014-12-30 22:53:19 +080020DECLARE_GLOBAL_DATA_PTR;
21
Simon Glass6fb3b722014-11-12 22:42:14 -070022static struct pci_controller *get_hose(void)
23{
Bin Meng8f9052f2014-12-30 22:53:21 +080024 if (gd->hose)
25 return gd->hose;
Simon Glass6fb3b722014-11-12 22:42:14 -070026
27 return pci_bus_to_hose(0);
28}
29
Simon Glass31f57c22015-03-05 12:25:15 -070030unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where)
Simon Glass6fb3b722014-11-12 22:42:14 -070031{
32 uint8_t value;
33
Simon Glass052e34b2015-08-12 20:09:30 -060034 if (pci_hose_read_config_byte(get_hose(), dev, where, &value))
35 return -1U;
Simon Glass6fb3b722014-11-12 22:42:14 -070036
37 return value;
38}
39
Simon Glass31f57c22015-03-05 12:25:15 -070040unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where)
Simon Glass6fb3b722014-11-12 22:42:14 -070041{
42 uint16_t value;
43
Simon Glass052e34b2015-08-12 20:09:30 -060044 if (pci_hose_read_config_word(get_hose(), dev, where, &value))
45 return -1U;
Simon Glass6fb3b722014-11-12 22:42:14 -070046
47 return value;
48}
49
Simon Glass31f57c22015-03-05 12:25:15 -070050unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where)
Simon Glass6fb3b722014-11-12 22:42:14 -070051{
52 uint32_t value;
53
Simon Glass052e34b2015-08-12 20:09:30 -060054 if (pci_hose_read_config_dword(get_hose(), dev, where, &value))
55 return -1U;
Simon Glass6fb3b722014-11-12 22:42:14 -070056
57 return value;
58}
59
Simon Glass31f57c22015-03-05 12:25:15 -070060void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
Simon Glass6fb3b722014-11-12 22:42:14 -070061{
62 pci_hose_write_config_byte(get_hose(), dev, where, value);
63}
64
Simon Glass31f57c22015-03-05 12:25:15 -070065void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
Simon Glass6fb3b722014-11-12 22:42:14 -070066{
67 pci_hose_write_config_word(get_hose(), dev, where, value);
68}
69
Simon Glass31f57c22015-03-05 12:25:15 -070070void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
Simon Glass6fb3b722014-11-12 22:42:14 -070071{
72 pci_hose_write_config_dword(get_hose(), dev, where, value);
73}
Simon Glassa219dae2015-03-05 12:25:31 -070074
75int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
76 ulong *valuep, enum pci_size_t size)
77{
78 outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
79 switch (size) {
80 case PCI_SIZE_8:
81 *valuep = inb(PCI_REG_DATA + (offset & 3));
82 break;
83 case PCI_SIZE_16:
84 *valuep = inw(PCI_REG_DATA + (offset & 2));
85 break;
86 case PCI_SIZE_32:
87 *valuep = inl(PCI_REG_DATA);
88 break;
89 }
90
91 return 0;
92}
93
94int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
95 ulong value, enum pci_size_t size)
96{
97 outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
98 switch (size) {
99 case PCI_SIZE_8:
100 outb(value, PCI_REG_DATA + (offset & 3));
101 break;
102 case PCI_SIZE_16:
103 outw(value, PCI_REG_DATA + (offset & 2));
104 break;
105 case PCI_SIZE_32:
106 outl(value, PCI_REG_DATA);
107 break;
108 }
109
110 return 0;
111}
Bin Menge3e7fa22015-04-24 18:10:03 +0800112
Bin Meng31a2dc62015-07-15 16:23:40 +0800113void pci_assign_irqs(int bus, int device, u8 irq[4])
Bin Menge3e7fa22015-04-24 18:10:03 +0800114{
115 pci_dev_t bdf;
Bin Meng31a2dc62015-07-15 16:23:40 +0800116 int func;
117 u16 vendor;
Bin Menge3e7fa22015-04-24 18:10:03 +0800118 u8 pin, line;
119
Bin Meng31a2dc62015-07-15 16:23:40 +0800120 for (func = 0; func < 8; func++) {
121 bdf = PCI_BDF(bus, device, func);
122 vendor = x86_pci_read_config16(bdf, PCI_VENDOR_ID);
123 if (vendor == 0xffff || vendor == 0x0000)
124 continue;
Bin Menge3e7fa22015-04-24 18:10:03 +0800125
Bin Meng31a2dc62015-07-15 16:23:40 +0800126 pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN);
Bin Menge3e7fa22015-04-24 18:10:03 +0800127
Bin Meng31a2dc62015-07-15 16:23:40 +0800128 /* PCI spec says all values except 1..4 are reserved */
129 if ((pin < 1) || (pin > 4))
130 continue;
Bin Menge3e7fa22015-04-24 18:10:03 +0800131
Bin Meng31a2dc62015-07-15 16:23:40 +0800132 line = irq[pin - 1];
Bin Meng6fc0e8a2015-07-15 16:23:41 +0800133 if (!line)
134 continue;
Bin Menge3e7fa22015-04-24 18:10:03 +0800135
Bin Meng31a2dc62015-07-15 16:23:40 +0800136 debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n",
137 line, bus, device, func, 'A' + pin - 1);
Bin Menge3e7fa22015-04-24 18:10:03 +0800138
Bin Meng31a2dc62015-07-15 16:23:40 +0800139 x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line);
140 }
Bin Menge3e7fa22015-04-24 18:10:03 +0800141}