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Dirk Behmead9bc8e2009-01-28 21:39:58 +01001/*
2 * (C) Copyright 2004-2008
3 * Texas Instruments, <www.ti.com>
4 *
5 * Author :
6 * Manikandan Pillai <mani.pillai@ti.com>
7 *
8 * Derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30#include <common.h>
31#include <asm/io.h>
32#include <asm/arch/mem.h>
33#include <asm/arch/mux.h>
34#include <asm/arch/sys_proto.h>
35#include <i2c.h>
36#include <asm/mach-types.h>
37#include "evm.h"
38
39/******************************************************************************
40 * Routine: board_init
41 * Description: Early hardware init.
42 *****************************************************************************/
43int board_init(void)
44{
45 DECLARE_GLOBAL_DATA_PTR;
46
47 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
48 /* board id for Linux */
49 gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
50 /* boot param addr */
51 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
52
53 return 0;
54}
55
56/******************************************************************************
57 * Routine: misc_init_r
58 * Description: Init ethernet (done here so udelay works)
59 *****************************************************************************/
60int misc_init_r(void)
61{
62
63#ifdef CONFIG_DRIVER_OMAP34XX_I2C
64 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
65#endif
66
67#if defined(CONFIG_CMD_NET)
68 setup_net_chip();
69#endif
70
Dirk Behmee6a6a702009-03-12 19:30:50 +010071 dieid_num_r();
72
Dirk Behmead9bc8e2009-01-28 21:39:58 +010073 return 0;
74}
75
76/******************************************************************************
77 * Routine: set_muxconf_regs
78 * Description: Setting up the configuration Mux registers specific to the
79 * hardware. Many pins need to be moved from protect to primary
80 * mode.
81 *****************************************************************************/
82void set_muxconf_regs(void)
83{
84 MUX_EVM();
85}
86
87/******************************************************************************
88 * Routine: setup_net_chip
89 * Description: Setting up the configuration GPMC registers specific to the
90 * Ethernet hardware.
91 *****************************************************************************/
92static void setup_net_chip(void)
93{
94 gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE;
95 gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE;
96 ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
97
98 /* Configure GPMC registers */
99 writel(NET_GPMC_CONFIG1, &gpmc_cs6_base->config1);
100 writel(NET_GPMC_CONFIG2, &gpmc_cs6_base->config2);
101 writel(NET_GPMC_CONFIG3, &gpmc_cs6_base->config3);
102 writel(NET_GPMC_CONFIG4, &gpmc_cs6_base->config4);
103 writel(NET_GPMC_CONFIG5, &gpmc_cs6_base->config5);
104 writel(NET_GPMC_CONFIG6, &gpmc_cs6_base->config6);
105 writel(NET_GPMC_CONFIG7, &gpmc_cs6_base->config7);
106
107 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
108 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
109 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
110 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
111 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
112 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
113 &ctrl_base->gpmc_nadv_ale);
114
115 /* Make GPIO 64 as output pin */
116 writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe);
117
118 /* Now send a pulse on the GPIO pin */
119 writel(GPIO0, &gpio3_base->setdataout);
120 udelay(1);
121 writel(GPIO0, &gpio3_base->cleardataout);
122 udelay(1);
123 writel(GPIO0, &gpio3_base->setdataout);
124}