Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / e264e3cc5be81548c6f102b6b597a474e5bd4f20 / . / arch / x86 / dts / conga-qeval20-qa3-e3845.dts
blob: 7e69ba487302bdb1230c6e686545594a11489722 [file] [log] [blame]
Stefan Roese82ceba22016-03-16 08:48:21 +0100[diff] [blame]1/*
2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8/dts-v1/;
9
10#include <dt-bindings/gpio/x86-gpio.h>
11#include <dt-bindings/interrupt-router/intel-irq.h>
12
13/include/ "skeleton.dtsi"
14/include/ "serial.dtsi"
15/include/ "rtc.dtsi"
16/include/ "tsc_timer.dtsi"
17
18/ {
19 model = "congatec-QEVAL20-QA3-E3845";
20 compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail";
21
22 aliases {
23 serial0 = &serial;
24 spi0 = &spi;
25 };
26
27 config {
28 silent_console = <0>;
29 };
30
31 pch_pinctrl {
32 compatible = "intel,x86-pinctrl";
Bin Menge264e3c2016-06-08 05:07:33 -0700[diff] [blame^]33 reg = <0 0>;
Stefan Roese82ceba22016-03-16 08:48:21 +0100[diff] [blame]34 };
35
36 chosen {
37 stdout-path = "/serial";
38 };
39
40 cpus {
41 #address-cells = <1>;
42 #size-cells = <0>;
43
44 cpu@0 {
45 device_type = "cpu";
46 compatible = "intel,baytrail-cpu";
47 reg = <0>;
48 intel,apic-id = <0>;
49 };
50
51 cpu@1 {
52 device_type = "cpu";
53 compatible = "intel,baytrail-cpu";
54 reg = <1>;
55 intel,apic-id = <2>;
56 };
57
58 cpu@2 {
59 device_type = "cpu";
60 compatible = "intel,baytrail-cpu";
61 reg = <2>;
62 intel,apic-id = <4>;
63 };
64
65 cpu@3 {
66 device_type = "cpu";
67 compatible = "intel,baytrail-cpu";
68 reg = <3>;
69 intel,apic-id = <6>;
70 };
71 };
72
73 pci {
74 compatible = "intel,pci-baytrail", "pci-x86";
75 #address-cells = <3>;
76 #size-cells = <2>;
77 u-boot,dm-pre-reloc;
78 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
79 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
80 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
81
82 pch@1f,0 {
83 reg = <0x0000f800 0 0 0 0>;
84 compatible = "pci8086,0f1c", "intel,pch9";
85 #address-cells = <1>;
86 #size-cells = <1>;
87
88 irq-router {
89 compatible = "intel,irq-router";
90 intel,pirq-config = "ibase";
91 intel,ibase-offset = <0x50>;
Bin Mengce8dd772016-05-07 07:46:15 -0700[diff] [blame]92 intel,actl-addr = <0>;
Stefan Roese82ceba22016-03-16 08:48:21 +0100[diff] [blame]93 intel,pirq-link = <8 8>;
94 intel,pirq-mask = <0xdee0>;
95 intel,pirq-routing = <
96 /* BayTrail PCI devices */
97 PCI_BDF(0, 2, 0) INTA PIRQA
98 PCI_BDF(0, 3, 0) INTA PIRQA
99 PCI_BDF(0, 16, 0) INTA PIRQA
100 PCI_BDF(0, 17, 0) INTA PIRQA
101 PCI_BDF(0, 18, 0) INTA PIRQA
102 PCI_BDF(0, 19, 0) INTA PIRQA
103 PCI_BDF(0, 20, 0) INTA PIRQA
104 PCI_BDF(0, 21, 0) INTA PIRQA
105 PCI_BDF(0, 22, 0) INTA PIRQA
106 PCI_BDF(0, 23, 0) INTA PIRQA
107 PCI_BDF(0, 24, 0) INTA PIRQA
108 PCI_BDF(0, 24, 1) INTC PIRQC
109 PCI_BDF(0, 24, 2) INTD PIRQD
110 PCI_BDF(0, 24, 3) INTB PIRQB
111 PCI_BDF(0, 24, 4) INTA PIRQA
112 PCI_BDF(0, 24, 5) INTC PIRQC
113 PCI_BDF(0, 24, 6) INTD PIRQD
114 PCI_BDF(0, 24, 7) INTB PIRQB
115 PCI_BDF(0, 26, 0) INTA PIRQA
116 PCI_BDF(0, 27, 0) INTA PIRQA
117 PCI_BDF(0, 28, 0) INTA PIRQA
118 PCI_BDF(0, 28, 1) INTB PIRQB
119 PCI_BDF(0, 28, 2) INTC PIRQC
120 PCI_BDF(0, 28, 3) INTD PIRQD
121 PCI_BDF(0, 29, 0) INTA PIRQA
122 PCI_BDF(0, 30, 0) INTA PIRQA
123 PCI_BDF(0, 30, 1) INTD PIRQD
124 PCI_BDF(0, 30, 2) INTB PIRQB
125 PCI_BDF(0, 30, 3) INTC PIRQC
126 PCI_BDF(0, 30, 4) INTD PIRQD
127 PCI_BDF(0, 30, 5) INTB PIRQB
128 PCI_BDF(0, 31, 3) INTB PIRQB
129
130 /*
131 * PCIe root ports downstream
132 * interrupts
133 */
134 PCI_BDF(1, 0, 0) INTA PIRQA
135 PCI_BDF(1, 0, 0) INTB PIRQB
136 PCI_BDF(1, 0, 0) INTC PIRQC
137 PCI_BDF(1, 0, 0) INTD PIRQD
138 PCI_BDF(2, 0, 0) INTA PIRQB
139 PCI_BDF(2, 0, 0) INTB PIRQC
140 PCI_BDF(2, 0, 0) INTC PIRQD
141 PCI_BDF(2, 0, 0) INTD PIRQA
142 PCI_BDF(3, 0, 0) INTA PIRQC
143 PCI_BDF(3, 0, 0) INTB PIRQD
144 PCI_BDF(3, 0, 0) INTC PIRQA
145 PCI_BDF(3, 0, 0) INTD PIRQB
146 PCI_BDF(4, 0, 0) INTA PIRQD
147 PCI_BDF(4, 0, 0) INTB PIRQA
148 PCI_BDF(4, 0, 0) INTC PIRQB
149 PCI_BDF(4, 0, 0) INTD PIRQC
150 >;
151 };
152
153 spi: spi {
154 #address-cells = <1>;
155 #size-cells = <0>;
156 compatible = "intel,ich9-spi";
157 spi-flash@0 {
158 #address-cells = <1>;
159 #size-cells = <1>;
160 reg = <0>;
161 compatible = "stmicro,n25q064a",
162 "spi-flash";
163 memory-map = <0xff800000 0x00800000>;
164 rw-mrc-cache {
165 label = "rw-mrc-cache";
166 reg = <0x006f0000 0x00010000>;
167 };
168 };
169 };
170
171 gpioa {
172 compatible = "intel,ich6-gpio";
173 u-boot,dm-pre-reloc;
174 reg = <0 0x20>;
175 bank-name = "A";
176 };
177
178 gpiob {
179 compatible = "intel,ich6-gpio";
180 u-boot,dm-pre-reloc;
181 reg = <0x20 0x20>;
182 bank-name = "B";
183 };
184
185 gpioc {
186 compatible = "intel,ich6-gpio";
187 u-boot,dm-pre-reloc;
188 reg = <0x40 0x20>;
189 bank-name = "C";
190 };
191
192 gpiod {
193 compatible = "intel,ich6-gpio";
194 u-boot,dm-pre-reloc;
195 reg = <0x60 0x20>;
196 bank-name = "D";
197 };
198
199 gpioe {
200 compatible = "intel,ich6-gpio";
201 u-boot,dm-pre-reloc;
202 reg = <0x80 0x20>;
203 bank-name = "E";
204 };
205
206 gpiof {
207 compatible = "intel,ich6-gpio";
208 u-boot,dm-pre-reloc;
209 reg = <0xA0 0x20>;
210 bank-name = "F";
211 };
212 };
213 };
214
215 fsp {
216 compatible = "intel,baytrail-fsp";
217 fsp,mrc-init-tseg-size = <0>;
218 fsp,mrc-init-mmio-size = <0x800>;
219 fsp,mrc-init-spd-addr1 = <0xa0>;
220 fsp,mrc-init-spd-addr2 = <0xa2>;
221 fsp,emmc-boot-mode = <2>;
222 fsp,enable-sdio;
223 fsp,enable-sdcard;
224 fsp,enable-hsuart1;
225 fsp,enable-spi;
226 fsp,enable-sata;
227 fsp,sata-mode = <1>;
228 fsp,enable-lpe;
229 fsp,lpss-sio-enable-pci-mode;
230 fsp,enable-dma0;
231 fsp,enable-dma1;
232 fsp,enable-i2c0;
233 fsp,enable-i2c1;
234 fsp,enable-i2c2;
235 fsp,enable-i2c3;
236 fsp,enable-i2c4;
237 fsp,enable-i2c5;
238 fsp,enable-i2c6;
239 fsp,enable-pwm0;
240 fsp,enable-pwm1;
241 fsp,igd-dvmt50-pre-alloc = <2>;
242 fsp,aperture-size = <2>;
243 fsp,gtt-size = <2>;
244 fsp,scc-enable-pci-mode;
245 fsp,os-selection = <4>;
246 fsp,emmc45-ddr50-enabled;
247 fsp,emmc45-retune-timer-value = <8>;
248 fsp,enable-igd;
249 fsp,enable-memory-down;
250 fsp,memory-down-params {
251 compatible = "intel,baytrail-fsp-mdp";
252 fsp,dram-speed = <2>; /* 2=1333MHz */
253 fsp,dram-type = <1>; /* 1=DDR3L */
254 fsp,dimm-0-enable;
255 fsp,dimm-1-enable;
256 fsp,dimm-width = <1>; /* 1=x16, 2=x32 */
257 fsp,dimm-density = <2>; /* 2=4Gbit */
258 fsp,dimm-bus-width = <3>; /* 3=64bits */
259 fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */
260
261 /* These following values might need a re-visit */
262 fsp,dimm-tcl = <8>;
263 fsp,dimm-trpt-rcd = <8>;
264 fsp,dimm-twr = <8>;
265 fsp,dimm-twtr = <4>;
266 fsp,dimm-trrd = <6>;
267 fsp,dimm-trtp = <4>;
268 fsp,dimm-tfaw = <22>;
269 };
270 };
271
272 microcode {
273 update@0 {
Bin Mengbab4b962016-05-23 15:25:20 +0800[diff] [blame]274#include "microcode/m0130673325.dtsi"
Stefan Roese82ceba22016-03-16 08:48:21 +0100[diff] [blame]275 };
276 update@1 {
Bin Mengbab4b962016-05-23 15:25:20 +0800[diff] [blame]277#include "microcode/m0130679907.dtsi"
Stefan Roese82ceba22016-03-16 08:48:21 +0100[diff] [blame]278 };
279 };
280};