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Tom Warrenb2871032012-12-11 13:34:15 +00001/*
Jimmy Zhangb9dd6212014-01-24 10:37:36 -07002 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
Tom Warrenb2871032012-12-11 13:34:15 +00003 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/* Tegra30 Clock control functions */
18
19#include <common.h>
Thierry Redinga7230742014-12-09 22:25:06 -070020#include <errno.h>
Tom Warrenb2871032012-12-11 13:34:15 +000021#include <asm/io.h>
22#include <asm/arch/clock.h>
23#include <asm/arch/tegra.h>
24#include <asm/arch-tegra/clk_rst.h>
25#include <asm/arch-tegra/timer.h>
26#include <div64.h>
27#include <fdtdec.h>
28
29/*
Tom Warrenf29f0862013-01-23 14:01:01 -070030 * Clock types that we can use as a source. The Tegra30 has muxes for the
Tom Warrenb2871032012-12-11 13:34:15 +000031 * peripheral clocks, and in most cases there are four options for the clock
32 * source. This gives us a clock 'type' and exploits what commonality exists
33 * in the device.
34 *
35 * Letters are obvious, except for T which means CLK_M, and S which means the
36 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
37 * datasheet) and PLL_M are different things. The former is the basic
38 * clock supplied to the SOC from an external oscillator. The latter is the
39 * memory clock PLL.
40 *
41 * See definitions in clock_id in the header file.
42 */
43enum clock_type_id {
44 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
45 CLOCK_TYPE_MCPA, /* and so on */
46 CLOCK_TYPE_MCPT,
47 CLOCK_TYPE_PCM,
48 CLOCK_TYPE_PCMT,
Tom Warren619bd992012-12-21 15:02:45 -070049 CLOCK_TYPE_PCMT16,
Tom Warrenb2871032012-12-11 13:34:15 +000050 CLOCK_TYPE_PDCT,
51 CLOCK_TYPE_ACPT,
52 CLOCK_TYPE_ASPTE,
53 CLOCK_TYPE_PMDACD2T,
54 CLOCK_TYPE_PCST,
55
56 CLOCK_TYPE_COUNT,
Tom Warrenf29f0862013-01-23 14:01:01 -070057 CLOCK_TYPE_NONE = -1, /* invalid clock type */
Tom Warrenb2871032012-12-11 13:34:15 +000058};
59
60enum {
Tom Warrenf29f0862013-01-23 14:01:01 -070061 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
62};
63
Tom Warrenb2871032012-12-11 13:34:15 +000064/*
65 * Clock source mux for each clock type. This just converts our enum into
66 * a list of mux sources for use by the code.
67 *
68 * Note:
69 * The extra column in each clock source array is used to store the mask
70 * bits in its register for the source.
71 */
72#define CLK(x) CLOCK_ID_ ## x
73static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
Tom Warrenf29f0862013-01-23 14:01:01 -070074 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
75 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +000076 MASK_BITS_31_30},
Tom Warrenf29f0862013-01-23 14:01:01 -070077 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
78 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +000079 MASK_BITS_31_30},
Tom Warrenf29f0862013-01-23 14:01:01 -070080 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
81 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +000082 MASK_BITS_31_30},
Tom Warrenf29f0862013-01-23 14:01:01 -070083 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
84 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +000085 MASK_BITS_31_30},
Tom Warrenf29f0862013-01-23 14:01:01 -070086 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
87 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +000088 MASK_BITS_31_30},
Tom Warrenf29f0862013-01-23 14:01:01 -070089 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
90 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warren619bd992012-12-21 15:02:45 -070091 MASK_BITS_31_30},
Tom Warrenf29f0862013-01-23 14:01:01 -070092 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
93 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +000094 MASK_BITS_31_30},
Tom Warrenf29f0862013-01-23 14:01:01 -070095 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
96 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +000097 MASK_BITS_31_30},
Tom Warrenf29f0862013-01-23 14:01:01 -070098 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
99 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +0000100 MASK_BITS_31_29},
Tom Warrenf29f0862013-01-23 14:01:01 -0700101 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
102 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +0000103 MASK_BITS_31_29},
Tom Warrenf29f0862013-01-23 14:01:01 -0700104 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
105 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Stephen Warren5916a362014-01-24 10:16:18 -0700106 MASK_BITS_31_28}
Tom Warrenb2871032012-12-11 13:34:15 +0000107};
108
Tom Warrenb2871032012-12-11 13:34:15 +0000109/*
110 * Clock type for each peripheral clock source. We put the name in each
111 * record just so it is easy to match things up
112 */
113#define TYPE(name, type) type
114static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
115 /* 0x00 */
116 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
Tom Warrenf29f0862013-01-23 14:01:01 -0700117 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
118 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
119 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
120 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
121 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
122 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
123 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
Tom Warrenb2871032012-12-11 13:34:15 +0000124
125 /* 0x08 */
Tom Warrenf29f0862013-01-23 14:01:01 -0700126 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
127 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
128 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
129 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
130 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
131 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
132 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
133 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
Tom Warrenb2871032012-12-11 13:34:15 +0000134
135 /* 0x10 */
Tom Warrenf29f0862013-01-23 14:01:01 -0700136 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
137 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
Tom Warrenb2871032012-12-11 13:34:15 +0000138 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
Tom Warrenf29f0862013-01-23 14:01:01 -0700139 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
140 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
Tom Warrenb2871032012-12-11 13:34:15 +0000141 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
142 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
143 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
144
145 /* 0x18 */
146 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
147 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
Tom Warrenf29f0862013-01-23 14:01:01 -0700148 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
149 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
150 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
151 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
152 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
153 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
Tom Warrenb2871032012-12-11 13:34:15 +0000154
155 /* 0x20 */
Tom Warrenf29f0862013-01-23 14:01:01 -0700156 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
157 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
158 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
159 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
160 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
161 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
162 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
Tom Warrenb2871032012-12-11 13:34:15 +0000163 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
164
165 /* 0x28 */
166 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
167 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
168 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
Tom Warrenf29f0862013-01-23 14:01:01 -0700169 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
170 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
171 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
172 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
173 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
Tom Warrenb2871032012-12-11 13:34:15 +0000174
175 /* 0x30 */
176 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
177 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
178 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
Tom Warrenf29f0862013-01-23 14:01:01 -0700179 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
180 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
181 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
182 TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
183 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
Tom Warrenb2871032012-12-11 13:34:15 +0000184
Tom Warrenf29f0862013-01-23 14:01:01 -0700185 /* 0x38h */ /* Jumps to reg offset 0x3B0h - new for T30 */
186 TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
187 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
188 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
189 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
190 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
191 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
192 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
193 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
Tom Warrenb2871032012-12-11 13:34:15 +0000194
195 /* 0x40 */
Tom Warrenf29f0862013-01-23 14:01:01 -0700196 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
197 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
198 TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
199 TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
200 TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
Tom Warrenb2871032012-12-11 13:34:15 +0000201 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
Tom Warrenf29f0862013-01-23 14:01:01 -0700202 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
Tom Warrenb2871032012-12-11 13:34:15 +0000203 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
204
205 /* 0x48 */
206 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
207 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
Tom Warrenf29f0862013-01-23 14:01:01 -0700208 TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
209 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
210 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
211 TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
212 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
213 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
Tom Warrenb2871032012-12-11 13:34:15 +0000214
215 /* 0x50 */
Tom Warrenf29f0862013-01-23 14:01:01 -0700216 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
217 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
218 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
219 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
220 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
221 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
222 TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
Tom Warrenb2871032012-12-11 13:34:15 +0000223};
224
225/*
226 * This array translates a periph_id to a periphc_internal_id
227 *
228 * Not present/matched up:
229 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
230 * SPDIF - which is both 0x08 and 0x0c
231 *
232 */
233#define NONE(name) (-1)
234#define OFFSET(name, value) PERIPHC_ ## name
235static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
236 /* Low word: 31:0 */
237 NONE(CPU),
238 NONE(COP),
239 NONE(TRIGSYS),
240 NONE(RESERVED3),
241 NONE(RESERVED4),
242 NONE(TMR),
243 PERIPHC_UART1,
Tom Warrenf29f0862013-01-23 14:01:01 -0700244 PERIPHC_UART2, /* and vfir 0x68 */
Tom Warrenb2871032012-12-11 13:34:15 +0000245
246 /* 8 */
247 NONE(GPIO),
248 PERIPHC_SDMMC2,
Tom Warrenf29f0862013-01-23 14:01:01 -0700249 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
Tom Warrenb2871032012-12-11 13:34:15 +0000250 PERIPHC_I2S1,
251 PERIPHC_I2C1,
252 PERIPHC_NDFLASH,
253 PERIPHC_SDMMC1,
254 PERIPHC_SDMMC4,
255
256 /* 16 */
257 NONE(RESERVED16),
258 PERIPHC_PWM,
259 PERIPHC_I2S2,
260 PERIPHC_EPP,
261 PERIPHC_VI,
262 PERIPHC_G2D,
263 NONE(USBD),
264 NONE(ISP),
265
266 /* 24 */
267 PERIPHC_G3D,
268 NONE(RESERVED25),
269 PERIPHC_DISP2,
270 PERIPHC_DISP1,
271 PERIPHC_HOST1X,
272 NONE(VCP),
273 PERIPHC_I2S0,
274 NONE(CACHE2),
275
276 /* Middle word: 63:32 */
277 NONE(MEM),
278 NONE(AHBDMA),
279 NONE(APBDMA),
280 NONE(RESERVED35),
281 NONE(RESERVED36),
282 NONE(STAT_MON),
283 NONE(RESERVED38),
284 NONE(RESERVED39),
285
286 /* 40 */
287 NONE(KFUSE),
Allen Martin7d54f022013-01-29 13:51:25 +0000288 PERIPHC_SBC1,
Tom Warrenb2871032012-12-11 13:34:15 +0000289 PERIPHC_NOR,
290 NONE(RESERVED43),
291 PERIPHC_SBC2,
292 NONE(RESERVED45),
293 PERIPHC_SBC3,
294 PERIPHC_DVC_I2C,
295
296 /* 48 */
297 NONE(DSI),
Tom Warrenf29f0862013-01-23 14:01:01 -0700298 PERIPHC_TVO, /* also CVE 0x40 */
Tom Warrenb2871032012-12-11 13:34:15 +0000299 PERIPHC_MIPI,
300 PERIPHC_HDMI,
301 NONE(CSI),
302 PERIPHC_TVDAC,
303 PERIPHC_I2C2,
304 PERIPHC_UART3,
305
306 /* 56 */
307 NONE(RESERVED56),
308 PERIPHC_EMC,
309 NONE(USB2),
310 NONE(USB3),
311 PERIPHC_MPE,
312 PERIPHC_VDE,
313 NONE(BSEA),
314 NONE(BSEV),
315
316 /* Upper word 95:64 */
317 PERIPHC_SPEEDO,
318 PERIPHC_UART4,
319 PERIPHC_UART5,
320 PERIPHC_I2C3,
321 PERIPHC_SBC4,
322 PERIPHC_SDMMC3,
323 NONE(PCIE),
324 PERIPHC_OWR,
325
326 /* 72 */
327 NONE(AFI),
328 PERIPHC_CSITE,
329 NONE(PCIEXCLK),
330 NONE(AVPUCQ),
331 NONE(RESERVED76),
332 NONE(RESERVED77),
333 NONE(RESERVED78),
334 NONE(DTV),
335
336 /* 80 */
337 PERIPHC_NANDSPEED,
338 PERIPHC_I2CSLOW,
339 NONE(DSIB),
340 NONE(RESERVED83),
341 NONE(IRAMA),
342 NONE(IRAMB),
343 NONE(IRAMC),
344 NONE(IRAMD),
345
346 /* 88 */
347 NONE(CRAM2),
348 NONE(RESERVED89),
349 NONE(MDOUBLER),
350 NONE(RESERVED91),
351 NONE(SUSOUT),
352 NONE(RESERVED93),
353 NONE(RESERVED94),
354 NONE(RESERVED95),
355
356 /* V word: 31:0 */
357 NONE(CPUG),
358 NONE(CPULP),
359 PERIPHC_G3D2,
360 PERIPHC_MSELECT,
361 PERIPHC_TSENSOR,
362 PERIPHC_I2S3,
363 PERIPHC_I2S4,
364 PERIPHC_I2C4,
365
366 /* 08 */
367 PERIPHC_SBC5,
368 PERIPHC_SBC6,
369 PERIPHC_AUDIO,
370 NONE(APBIF),
371 PERIPHC_DAM0,
372 PERIPHC_DAM1,
373 PERIPHC_DAM2,
374 PERIPHC_HDA2CODEC2X,
375
376 /* 16 */
377 NONE(ATOMICS),
378 NONE(RESERVED17),
379 NONE(RESERVED18),
380 NONE(RESERVED19),
381 NONE(RESERVED20),
382 NONE(RESERVED21),
383 NONE(RESERVED22),
384 PERIPHC_ACTMON,
385
386 /* 24 */
387 NONE(RESERVED24),
388 NONE(RESERVED25),
389 NONE(RESERVED26),
390 NONE(RESERVED27),
391 PERIPHC_SATA,
392 PERIPHC_HDA,
393 NONE(RESERVED30),
394 NONE(RESERVED31),
395
396 /* W word: 31:0 */
397 NONE(HDA2HDMICODEC),
398 NONE(SATACOLD),
399 NONE(RESERVED0_PCIERX0),
400 NONE(RESERVED1_PCIERX1),
401 NONE(RESERVED2_PCIERX2),
402 NONE(RESERVED3_PCIERX3),
403 NONE(RESERVED4_PCIERX4),
404 NONE(RESERVED5_PCIERX5),
405
406 /* 40 */
407 NONE(CEC),
408 NONE(RESERVED6_PCIE2),
409 NONE(RESERVED7_EMC),
410 NONE(RESERVED8_HDMI),
411 NONE(RESERVED9_SATA),
412 NONE(RESERVED10_MIPI),
413 NONE(EX_RESERVED46),
414 NONE(EX_RESERVED47),
415};
416
417/*
418 * Get the oscillator frequency, from the corresponding hardware configuration
Tom Warrenf29f0862013-01-23 14:01:01 -0700419 * field. Note that T30 supports 3 new higher freqs, but we map back
420 * to the old T20 freqs. Support for the higher oscillators is TBD.
Tom Warrenb2871032012-12-11 13:34:15 +0000421 */
422enum clock_osc_freq clock_get_osc_freq(void)
423{
424 struct clk_rst_ctlr *clkrst =
425 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
426 u32 reg;
427
428 reg = readl(&clkrst->crc_osc_ctrl);
Tom Warrenf29f0862013-01-23 14:01:01 -0700429 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
Tom Warrenb2871032012-12-11 13:34:15 +0000430
Tom Warrenf29f0862013-01-23 14:01:01 -0700431 if (reg & 1) /* one of the newer freqs */
432 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
Tom Warrenb2871032012-12-11 13:34:15 +0000433
Tom Warrenf29f0862013-01-23 14:01:01 -0700434 return reg >> 2; /* Map to most common (T20) freqs */
Tom Warrenb2871032012-12-11 13:34:15 +0000435}
436
437/* Returns a pointer to the clock source register for a peripheral */
Tom Warrenf29f0862013-01-23 14:01:01 -0700438u32 *get_periph_source_reg(enum periph_id periph_id)
Tom Warrenb2871032012-12-11 13:34:15 +0000439{
440 struct clk_rst_ctlr *clkrst =
Tom Warrenf29f0862013-01-23 14:01:01 -0700441 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
Tom Warrenb2871032012-12-11 13:34:15 +0000442 enum periphc_internal_id internal_id;
443
444 /* Coresight is a special case */
445 if (periph_id == PERIPH_ID_CSI)
446 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
447
448 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
449 internal_id = periph_id_to_internal_id[periph_id];
450 assert(internal_id != -1);
451 if (internal_id >= PERIPHC_VW_FIRST) {
452 internal_id -= PERIPHC_VW_FIRST;
453 return &clkrst->crc_clk_src_vw[internal_id];
454 } else
455 return &clkrst->crc_clk_src[internal_id];
456}
457
Tom Warrenb2871032012-12-11 13:34:15 +0000458/**
459 * Given a peripheral ID and the required source clock, this returns which
460 * value should be programmed into the source mux for that peripheral.
461 *
462 * There is special code here to handle the one source type with 5 sources.
463 *
464 * @param periph_id peripheral to start
465 * @param source PLL id of required parent clock
466 * @param mux_bits Set to number of bits in mux register: 2 or 4
Tom Warrenf29f0862013-01-23 14:01:01 -0700467 * @param divider_bits Set to number of divider bits (8 or 16)
Tom Warrenb2871032012-12-11 13:34:15 +0000468 * @return mux value (0-4, or -1 if not found)
469 */
Tom Warrenf29f0862013-01-23 14:01:01 -0700470int get_periph_clock_source(enum periph_id periph_id,
471 enum clock_id parent, int *mux_bits, int *divider_bits)
Tom Warrenb2871032012-12-11 13:34:15 +0000472{
473 enum clock_type_id type;
474 enum periphc_internal_id internal_id;
475 int mux;
476
477 assert(clock_periph_id_isvalid(periph_id));
478
479 internal_id = periph_id_to_internal_id[periph_id];
480 assert(periphc_internal_id_isvalid(internal_id));
481
482 type = clock_periph_type[internal_id];
483 assert(clock_type_id_isvalid(type));
484
485 *mux_bits = clock_source[type][CLOCK_MAX_MUX];
486
Tom Warren619bd992012-12-21 15:02:45 -0700487 if (type == CLOCK_TYPE_PCMT16)
488 *divider_bits = 16;
489 else
490 *divider_bits = 8;
491
Tom Warrenb2871032012-12-11 13:34:15 +0000492 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
493 if (clock_source[type][mux] == parent)
494 return mux;
495
496 /* if we get here, either us or the caller has made a mistake */
497 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
498 parent);
499 return -1;
500}
501
Tom Warrenb2871032012-12-11 13:34:15 +0000502void clock_set_enable(enum periph_id periph_id, int enable)
503{
504 struct clk_rst_ctlr *clkrst =
505 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
506 u32 *clk;
507 u32 reg;
508
509 /* Enable/disable the clock to this peripheral */
510 assert(clock_periph_id_isvalid(periph_id));
511 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
512 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
513 else
514 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
515 reg = readl(clk);
516 if (enable)
517 reg |= PERIPH_MASK(periph_id);
518 else
519 reg &= ~PERIPH_MASK(periph_id);
520 writel(reg, clk);
521}
522
Tom Warrenb2871032012-12-11 13:34:15 +0000523void reset_set_enable(enum periph_id periph_id, int enable)
524{
525 struct clk_rst_ctlr *clkrst =
526 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
527 u32 *reset;
528 u32 reg;
529
530 /* Enable/disable reset to the peripheral */
531 assert(clock_periph_id_isvalid(periph_id));
532 if (periph_id < PERIPH_ID_VW_FIRST)
533 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
534 else
535 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
536 reg = readl(reset);
537 if (enable)
538 reg |= PERIPH_MASK(periph_id);
539 else
540 reg &= ~PERIPH_MASK(periph_id);
541 writel(reg, reset);
542}
543
Tom Warrenb2871032012-12-11 13:34:15 +0000544#ifdef CONFIG_OF_CONTROL
545/*
546 * Convert a device tree clock ID to our peripheral ID. They are mostly
547 * the same but we are very cautious so we check that a valid clock ID is
548 * provided.
549 *
Tom Warren619bd992012-12-21 15:02:45 -0700550 * @param clk_id Clock ID according to tegra30 device tree binding
Tom Warrenb2871032012-12-11 13:34:15 +0000551 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
552 */
Tom Warrenf29f0862013-01-23 14:01:01 -0700553enum periph_id clk_id_to_periph_id(int clk_id)
Tom Warrenb2871032012-12-11 13:34:15 +0000554{
Tom Warren619bd992012-12-21 15:02:45 -0700555 if (clk_id > PERIPH_ID_COUNT)
Tom Warrenb2871032012-12-11 13:34:15 +0000556 return PERIPH_ID_NONE;
557
558 switch (clk_id) {
Tom Warren619bd992012-12-21 15:02:45 -0700559 case PERIPH_ID_RESERVED3:
560 case PERIPH_ID_RESERVED4:
561 case PERIPH_ID_RESERVED16:
562 case PERIPH_ID_RESERVED24:
563 case PERIPH_ID_RESERVED35:
564 case PERIPH_ID_RESERVED43:
565 case PERIPH_ID_RESERVED45:
566 case PERIPH_ID_RESERVED56:
Thierry Reding59cb3bf2014-12-09 22:25:07 -0700567 case PERIPH_ID_PCIEXCLK:
Tom Warren619bd992012-12-21 15:02:45 -0700568 case PERIPH_ID_RESERVED76:
569 case PERIPH_ID_RESERVED77:
570 case PERIPH_ID_RESERVED78:
571 case PERIPH_ID_RESERVED83:
572 case PERIPH_ID_RESERVED89:
573 case PERIPH_ID_RESERVED91:
574 case PERIPH_ID_RESERVED93:
575 case PERIPH_ID_RESERVED94:
576 case PERIPH_ID_RESERVED95:
Tom Warrenb2871032012-12-11 13:34:15 +0000577 return PERIPH_ID_NONE;
578 default:
579 return clk_id;
580 }
581}
Tom Warrenb2871032012-12-11 13:34:15 +0000582#endif /* CONFIG_OF_CONTROL */
583
Tom Warrenb2871032012-12-11 13:34:15 +0000584void clock_early_init(void)
585{
Jimmy Zhangb9dd6212014-01-24 10:37:36 -0700586 tegra30_set_up_pllp();
Tom Warrenb2871032012-12-11 13:34:15 +0000587}
Tom Warrenb40f7342013-04-01 15:48:54 -0700588
589void arch_timer_init(void)
590{
591}
Thierry Redinga7230742014-12-09 22:25:06 -0700592
593#define PMC_SATA_PWRGT 0x1ac
594#define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
595#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
596
597#define PLLE_SS_CNTL 0x68
598#define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
599#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
600#define PLLE_SS_CNTL_SSCBYP (1 << 12)
601#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
602#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
603#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
604
605#define PLLE_BASE 0x0e8
606#define PLLE_BASE_ENABLE_CML (1 << 31)
607#define PLLE_BASE_ENABLE (1 << 30)
608#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
609#define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
610#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
611#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
612
613#define PLLE_MISC 0x0ec
614#define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
615#define PLLE_MISC_PLL_READY (1 << 15)
616#define PLLE_MISC_LOCK (1 << 11)
617#define PLLE_MISC_LOCK_ENABLE (1 << 9)
618#define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
619
620static int tegra_plle_train(void)
621{
622 unsigned int timeout = 2000;
623 unsigned long value;
624
625 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
626 value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
627 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
628
629 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
630 value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
631 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
632
633 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
634 value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
635 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
636
637 do {
638 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
639 if (value & PLLE_MISC_PLL_READY)
640 break;
641
642 udelay(100);
643 } while (--timeout);
644
645 if (timeout == 0) {
646 error("timeout waiting for PLLE to become ready");
647 return -ETIMEDOUT;
648 }
649
650 return 0;
651}
652
653int tegra_plle_enable(void)
654{
655 unsigned int cpcon = 11, p = 18, n = 150, m = 1, timeout = 1000;
656 u32 value;
657 int err;
658
659 /* disable PLLE clock */
660 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
661 value &= ~PLLE_BASE_ENABLE_CML;
662 value &= ~PLLE_BASE_ENABLE;
663 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
664
665 /* clear lock enable and setup field */
666 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
667 value &= ~PLLE_MISC_LOCK_ENABLE;
668 value &= ~PLLE_MISC_SETUP_BASE(0xffff);
669 value &= ~PLLE_MISC_SETUP_EXT(0x3);
670 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
671
672 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
673 if ((value & PLLE_MISC_PLL_READY) == 0) {
674 err = tegra_plle_train();
675 if (err < 0) {
676 error("failed to train PLLE: %d", err);
677 return err;
678 }
679 }
680
681 /* configure PLLE */
682 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
683
684 value &= ~PLLE_BASE_PLDIV_CML(0x0f);
685 value |= PLLE_BASE_PLDIV_CML(cpcon);
686
687 value &= ~PLLE_BASE_PLDIV(0x3f);
688 value |= PLLE_BASE_PLDIV(p);
689
690 value &= ~PLLE_BASE_NDIV(0xff);
691 value |= PLLE_BASE_NDIV(n);
692
693 value &= ~PLLE_BASE_MDIV(0xff);
694 value |= PLLE_BASE_MDIV(m);
695
696 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
697
698 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
699 value |= PLLE_MISC_SETUP_BASE(0x7);
700 value |= PLLE_MISC_LOCK_ENABLE;
701 value |= PLLE_MISC_SETUP_EXT(0);
702 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
703
704 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
705 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
706 PLLE_SS_CNTL_BYPASS_SS;
707 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
708
709 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
710 value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
711 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
712
713 do {
714 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
715 if (value & PLLE_MISC_LOCK)
716 break;
717
718 udelay(2);
719 } while (--timeout);
720
721 if (timeout == 0) {
722 error("timeout waiting for PLLE to lock");
723 return -ETIMEDOUT;
724 }
725
726 udelay(50);
727
728 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
729 value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
730 value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
731
732 value &= ~PLLE_SS_CNTL_SSCINC(0xff);
733 value |= PLLE_SS_CNTL_SSCINC(0x01);
734
735 value &= ~PLLE_SS_CNTL_SSCBYP;
736 value &= ~PLLE_SS_CNTL_INTERP_RESET;
737 value &= ~PLLE_SS_CNTL_BYPASS_SS;
738
739 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
740 value |= PLLE_SS_CNTL_SSCMAX(0x24);
741 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
742
743 return 0;
744}