blob: 586a445f3ecc3ea97fd98074500e157c9dfd8745 [file] [log] [blame]
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -07001/*
2 * Aeronix Zipit Z2 configuration file
3 *
4 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*
13 * High Level Board Configuration Options
14 */
15#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
16#define CONFIG_SYS_TEXT_BASE 0x0
17
18#undef CONFIG_BOARD_LATE_INIT
19#undef CONFIG_SKIP_LOWLEVEL_INIT
20#define CONFIG_PREBOOT
21
22/*
23 * Environment settings
24 */
25#define CONFIG_ENV_OVERWRITE
26#define CONFIG_ENV_IS_IN_FLASH 1
27#define CONFIG_ENV_ADDR 0x40000
28#define CONFIG_ENV_SIZE 0x10000
29
30#define CONFIG_SYS_DCACHE_OFF
31
32#define CONFIG_SYS_MALLOC_LEN (128*1024)
33#define CONFIG_ARCH_CPU_INIT
34
35#define CONFIG_BOOTCOMMAND \
36 "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
37 "then " \
38 "source 0xa0000000; " \
39 "else " \
40 "bootm 0x50000; " \
41 "fi; "
42#define CONFIG_BOOTARGS \
43 "console=tty0 console=ttyS2,115200 fbcon=rotate:3"
44#define CONFIG_TIMESTAMP
45#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
46#define CONFIG_CMDLINE_TAG
47#define CONFIG_SETUP_MEMORY_TAGS
48#define CONFIG_SYS_TEXT_BASE 0x0
49#define CONFIG_LZMA /* LZMA compression support */
50
51/*
52 * Serial Console Configuration
53 * STUART - the lower serial port on Colibri board
54 */
55#define CONFIG_PXA_SERIAL
56#define CONFIG_STUART 1
57#define CONFIG_CONS_INDEX 2
58#define CONFIG_BAUDRATE 115200
59
60/*
61 * Bootloader Components Configuration
62 */
63#define CONFIG_CMD_ENV
64#define CONFIG_CMD_MMC
65#define CONFIG_CMD_SPI
66
67/*
68 * MMC Card Configuration
69 */
70#ifdef CONFIG_CMD_MMC
71#define CONFIG_MMC
72#define CONFIG_GENERIC_MMC
73#define CONFIG_PXA_MMC_GENERIC
74#define CONFIG_SYS_MMC_BASE 0xF0000000
75#define CONFIG_CMD_FAT
76#define CONFIG_CMD_EXT2
77#define CONFIG_DOS_PARTITION
78#endif
79
80/*
81 * SPI and LCD
82 */
83#ifdef CONFIG_CMD_SPI
84#define CONFIG_SOFT_SPI
85#define CONFIG_LCD
86#define CONFIG_PXA_LCD
87#define CONFIG_LMS283GF05
88
89#define SPI_DELAY udelay(10)
90#define SPI_SDA(val) zipitz2_spi_sda(val)
91#define SPI_SCL(val) zipitz2_spi_scl(val)
92#define SPI_READ zipitz2_spi_read()
93#ifndef __ASSEMBLY__
94void zipitz2_spi_sda(int);
95void zipitz2_spi_scl(int);
96unsigned char zipitz2_spi_read(void);
97#endif
98#endif
99
100/*
101 * HUSH Shell Configuration
102 */
103#define CONFIG_SYS_HUSH_PARSER 1
104
105#define CONFIG_SYS_LONGHELP /* undef to save memory */
106#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
107#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
108#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
109#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
110#define CONFIG_SYS_DEVICE_NULLDEV 1
111
112/*
113 * Clock Configuration
114 */
115#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
116
117/*
118 * SRAM Map
119 */
120#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
121#define PHYS_SRAM_SIZE 0x00040000 /* 256k */
122
123/*
124 * DRAM Map
125 */
126#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
127#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
128#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
129
130#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
131#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
132
133#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
134#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
135
136#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
137
138#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
139#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
140
141/*
142 * NOR FLASH
143 */
144#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
145#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
146#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
147#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
148
149#define CONFIG_SYS_FLASH_CFI
150#define CONFIG_FLASH_CFI_DRIVER 1
151#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
152
153#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
154#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
155
156#define CONFIG_SYS_MAX_FLASH_BANKS 1
157#define CONFIG_SYS_MAX_FLASH_SECT 256
158
159#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
160
161#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
162#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
163#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
164#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
165#define CONFIG_SYS_FLASH_PROTECTION
166
167/*
168 * GPIO settings
169 */
170#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
171#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
172#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
173#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
174#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
175#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
176#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
177#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
178#define CONFIG_SYS_GPCR0_VAL 0x00000000
179#define CONFIG_SYS_GPCR1_VAL 0x00000020
180#define CONFIG_SYS_GPCR2_VAL 0x00000000
181#define CONFIG_SYS_GPCR3_VAL 0x00000000
182#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
183#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
184#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
185#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
186#define CONFIG_SYS_GPSR0_VAL 0x06080400
187#define CONFIG_SYS_GPSR1_VAL 0x007f0000
188#define CONFIG_SYS_GPSR2_VAL 0x032a0000
189#define CONFIG_SYS_GPSR3_VAL 0x00000180
190
191#define CONFIG_SYS_PSSR_VAL 0x30
192
193/*
194 * Clock settings
195 */
196#define CONFIG_SYS_CKEN 0x00511220
197#define CONFIG_SYS_CCCR 0x00000190
198
199/*
200 * Memory settings
201 */
202#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
203#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
204#define CONFIG_SYS_MSC2_VAL 0x0000b884
205#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
206#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
207#define CONFIG_SYS_MDMRS_VAL 0x00000000
208#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
209#define CONFIG_SYS_SXCNFG_VAL 0x40044004
210
211/*
212 * PCMCIA and CF Interfaces
213 */
214#define CONFIG_SYS_MECR_VAL 0x00000001
215#define CONFIG_SYS_MCMEM0_VAL 0x00014307
216#define CONFIG_SYS_MCMEM1_VAL 0x00014307
217#define CONFIG_SYS_MCATT0_VAL 0x0001c787
218#define CONFIG_SYS_MCATT1_VAL 0x0001c787
219#define CONFIG_SYS_MCIO0_VAL 0x0001430f
220#define CONFIG_SYS_MCIO1_VAL 0x0001430f
221
222#include "pxa-common.h"
223
224#endif /* __CONFIG_H */