blob: 51814a677ff39d2dd68357d8e98f8e232ac97ce2 [file] [log] [blame]
Mike Frysinger581e97d2010-09-19 16:28:40 -04001/*
2 * U-boot - Configuration file for BF527 SDP board
3 */
4
5#ifndef __CONFIG_BF527_SDP_H__
6#define __CONFIG_BF527_SDP_H__
7
8#include <asm/config-pre.h>
9
10
11/*
12 * Processor Settings
13 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050014#define CONFIG_BFIN_CPU bf527-0.2
Mike Frysinger581e97d2010-09-19 16:28:40 -040015#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 24000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 25
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 5
40
41#define CONFIG_PLL_LOCKCNT_VAL 0x0200
42#define CONFIG_PLL_CTL_VAL 0x2a00
43#define CONFIG_VR_CTL_VAL 0x7090
44
45
46/*
47 * Memory Settings
48 */
49#define CONFIG_MEM_ADD_WDTH 9
50#define CONFIG_MEM_SIZE 32
51
52#define CONFIG_EBIU_SDRRC_VAL 0x00FE
53#define CONFIG_EBIU_SDGCTL_VAL 0x8011998d
54
55#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
56#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
57#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
58
59#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
60#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
61
62
63/*
64 * Flash Settings
65 */
66#define CONFIG_FLASH_CFI_DRIVER
67#define CONFIG_SYS_FLASH_BASE 0x20000000
68#define CONFIG_SYS_FLASH_CFI
69#define CONFIG_SYS_FLASH_PROTECTION
70#define CONFIG_SYS_MAX_FLASH_BANKS 1
71#define CONFIG_SYS_MAX_FLASH_SECT 259
72
73
74/*
75 * SPI Settings
76 */
77#define CONFIG_BFIN_SPI
78#define CONFIG_ENV_SPI_MAX_HZ 30000000
79#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysinger581e97d2010-09-19 16:28:40 -040080#define CONFIG_SPI_FLASH_ALL
81
82
83/*
84 * Env Storage Settings
85 */
86#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
87#define CONFIG_ENV_IS_IN_SPI_FLASH
88#define CONFIG_ENV_OFFSET 0x10000
89#define CONFIG_ENV_SIZE 0x2000
90#define CONFIG_ENV_SECT_SIZE 0x10000
91#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
92#else
93#define CONFIG_ENV_IS_IN_FLASH
94#define CONFIG_ENV_OFFSET 0x4000
95#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
96#define CONFIG_ENV_SIZE 0x2000
97#define CONFIG_ENV_SECT_SIZE 0x2000
98#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
99#endif
100
101
102/*
103 * I2C Settings
104 */
Scott Jiangc4697032014-11-13 15:30:55 +0800105#define CONFIG_SYS_I2C
Scott Jiangfea9b692014-11-13 15:30:53 +0800106#define CONFIG_SYS_I2C_ADI
Mike Frysinger581e97d2010-09-19 16:28:40 -0400107
108
109/*
110 * Misc Settings
111 */
112#define CONFIG_MISC_INIT_R
113#define CONFIG_UART_CONSOLE 0
Mike Frysinger581e97d2010-09-19 16:28:40 -0400114
115/*
116 * Pull in common ADI header for remaining command/environment setup
117 */
118#include <configs/bfin_adi_common.h>
119
120#endif