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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 5b060e465e0d286c271002c42bf8b274a0540692 / . / include / configs / ethernut5.h
blob: 3231f3cc0350e09a1fbc002b131b85f22f218f63 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]2/*
3 * (C) Copyright 2011
4 * egnite GmbH <info@egnite.de>
5 *
6 * Configuation settings for Ethernut 5 with AT91SAM9XE.
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include <asm/hardware.h>
13
14/* The first stage boot loader expects u-boot running at this address. */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]15
16/* The first stage boot loader takes care of low level initialization. */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]17
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]18/* CPU information */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]19
20/* ARM asynchronous clock */
21#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
22#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]23
24/* 32kB internal SRAM */
25#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
26#define CONFIG_SRAM_SIZE (32 << 10)
Rob Herring3d6ba912012-07-13 09:44:01 +0000[diff] [blame]27#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
28 GENERATED_GBL_DATA_SIZE)
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]29
30/* 128MB SDRAM in 1 bank */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]31#define CONFIG_SYS_SDRAM_BASE 0x20000000
32#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]33
34/* 512kB on-chip NOR flash */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]35# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]36# define CONFIG_SYS_MAX_FLASH_SECT 32
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]37# define CONFIG_EFLASH_PROTSECTORS 1
38
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]39
Wenyou.Yang@microchip.com94db5122017-07-21 14:30:57 +0800[diff] [blame]40/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]41
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]42/* NAND flash */
43#ifdef CONFIG_CMD_NAND
44#define CONFIG_SYS_MAX_NAND_DEVICE 1
45#define CONFIG_SYS_NAND_BASE 0x40000000
46#define CONFIG_SYS_NAND_DBW_8
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]47/* our ALE is AD21 */
48#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
49/* our CLE is AD22 */
50#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Andreas Bießmannac45bb12013-11-29 12:13:45 +0100[diff] [blame]51#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]52#endif
53
54/* JFFS2 */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]55
56/* Ethernet */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]57#define CONFIG_PHY_ID 0
58#define CONFIG_MACB_SEARCH_PHY
59
60/* MMC */
61#ifdef CONFIG_CMD_MMC
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]62#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
63#endif
64
65/* USB */
66#ifdef CONFIG_CMD_USB
67#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800[diff] [blame]68#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]69#define CONFIG_USB_OHCI_NEW
70#define CONFIG_SYS_USB_OHCI_CPU_INIT
71#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
72#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
73#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]74#endif
75
76/* RTC */
77#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]78#define CONFIG_SYS_I2C_RTC_ADDR 0x51
79#endif
80
81/* I2C */
82#define CONFIG_SYS_MAX_I2C_BUS 1
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]83
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]84#define I2C_SOFT_DECLARATIONS
85
86#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
87#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
88
89#define I2C_INIT { \
90 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
91 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
92 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
93 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
94 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
95}
96
97#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
98#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
99#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
100#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
101#define I2C_DELAY udelay(100)
102#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
103
104/* DHCP/BOOTP options */
105#ifdef CONFIG_CMD_DHCP
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]106#define CONFIG_SYS_AUTOLOAD "n"
107#endif
108
109/* File systems */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]110
111/* Boot command */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]112
113/* Misc. u-boot settings */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]114
115#endif