| Joel Stanley | 5bb26a5 | 2022-02-16 18:23:22 +1030 | [diff] [blame^] | 1 | menuconfig ASPEED_RAM |
| 2 | bool "ASPEED SDRAM configuration" |
| 3 | depends on RAM && ARCH_ASPEED |
| 4 | default ARCH_ASPEED |
| 5 | help |
| 6 | Configuration options for DDR SDRAM on ASPEED systems. |
| 7 | |
| 8 | RAM initialisation is always built in for the platform. This menu |
| 9 | allows customisation of the configuration used. |
| 10 | |
| 11 | if ASPEED_RAM |
| Dylan Hung | fde9314 | 2020-12-14 13:54:24 +0800 | [diff] [blame] | 12 | |
| Dylan Hung | 0474050 | 2020-09-07 16:25:07 +0800 | [diff] [blame] | 13 | config ASPEED_DDR4_DUALX8 |
| 14 | bool "Enable Dual X8 DDR4 die" |
| Joel Stanley | 5bb26a5 | 2022-02-16 18:23:22 +1030 | [diff] [blame^] | 15 | depends on ASPEED_RAM |
| Dylan Hung | 0474050 | 2020-09-07 16:25:07 +0800 | [diff] [blame] | 16 | help |
| Joel Stanley | 5bb26a5 | 2022-02-16 18:23:22 +1030 | [diff] [blame^] | 17 | Say Y if dual X8 DDR4 die is used on the board. The ASPEED DDRM |
| 18 | SRAM controller needs to know if the memory chip mounted on the |
| 19 | board is dual x8 die or not, otherwise it may get the wrong |
| 20 | size of the memory space. |
| Dylan Hung | fde9314 | 2020-12-14 13:54:24 +0800 | [diff] [blame] | 21 | |
| 22 | config ASPEED_BYPASS_SELFTEST |
| Joel Stanley | 5bb26a5 | 2022-02-16 18:23:22 +1030 | [diff] [blame^] | 23 | depends on ASPEED_RAM |
| 24 | depends on ASPEED_AST2600 |
| 25 | bool "Bypass self test during initialization" |
| Dylan Hung | fde9314 | 2020-12-14 13:54:24 +0800 | [diff] [blame] | 26 | help |
| Joel Stanley | 5bb26a5 | 2022-02-16 18:23:22 +1030 | [diff] [blame^] | 27 | Say Y here to bypass DRAM self test to speed up the boot time. |
| Dylan Hung | fde9314 | 2020-12-14 13:54:24 +0800 | [diff] [blame] | 28 | |
| 29 | config ASPEED_ECC |
| Joel Stanley | 5bb26a5 | 2022-02-16 18:23:22 +1030 | [diff] [blame^] | 30 | bool "ASPEED SDRAM ECC" |
| 31 | depends on ASPEED_RAM |
| 32 | depends on ASPEED_AST2600 |
| Dylan Hung | fde9314 | 2020-12-14 13:54:24 +0800 | [diff] [blame] | 33 | help |
| Joel Stanley | 5bb26a5 | 2022-02-16 18:23:22 +1030 | [diff] [blame^] | 34 | Enable SDRAM ECC function. This configures the SDRAM controller to |
| 35 | perform error detection and correction, sacrificing 1/9th of the |
| 36 | installed RAM to do so. |
| Dylan Hung | fde9314 | 2020-12-14 13:54:24 +0800 | [diff] [blame] | 37 | |
| Joel Stanley | 5bb26a5 | 2022-02-16 18:23:22 +1030 | [diff] [blame^] | 38 | |
| Dylan Hung | fde9314 | 2020-12-14 13:54:24 +0800 | [diff] [blame] | 39 | config ASPEED_ECC_SIZE |
| 40 | int "ECC size: 0=driver auto-caluated" |
| 41 | depends on ASPEED_ECC |
| 42 | default 0 |
| 43 | help |
| 44 | SDRAM size with the error correcting code enabled. The unit is |
| 45 | in Megabytes. Noted that only the 8/9 of the configured size |
| 46 | can be used by the system. The remaining 1/9 will be used by |
| 47 | the ECC engine. If the size is set to 0, the sdram driver will |
| 48 | calculate the SDRAM size and set the whole range be ECC enabled. |
| Joel Stanley | 5bb26a5 | 2022-02-16 18:23:22 +1030 | [diff] [blame^] | 49 | |
| 50 | choice |
| 51 | prompt "AST2600 DDR4 target date rate" |
| 52 | default ASPEED_DDR4_1600 |
| 53 | depends on ASPEED_RAM |
| 54 | depends on ASPEED_AST2600 |
| 55 | |
| 56 | config ASPEED_DDR4_400 |
| 57 | bool "400Mbps" |
| 58 | help |
| 59 | select DDR4 target data rate at 400M |
| 60 | |
| 61 | config ASPEED_DDR4_800 |
| 62 | bool "800Mbps" |
| 63 | help |
| 64 | select DDR4 target data rate at 800M |
| 65 | |
| 66 | config ASPEED_DDR4_1333 |
| 67 | bool "1333Mbps" |
| 68 | help |
| 69 | select DDR4 target data rate at 1333M |
| 70 | |
| 71 | config ASPEED_DDR4_1600 |
| 72 | bool "1600Mbps" |
| 73 | help |
| 74 | select DDR4 target data rate at 1600M |
| 75 | endchoice |
| 76 | |
| 77 | endif # End of ASPEED_RAM |