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Wenyou Yang2c4b2dd2016-07-25 17:46:17 +08001#include "skeleton.dtsi"
2
3/ {
4 model = "Atmel SAMA5D2 family SoC";
5 compatible = "atmel,sama5d2";
6
7 aliases {
8 spi0 = &spi0;
9 spi1 = &qspi0;
10 i2c0 = &i2c0;
11 i2c1 = &i2c1;
12 };
13
14 clocks {
15 slow_xtal: slow_xtal {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <0>;
19 };
20
21 main_xtal: main_xtal {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <0>;
25 };
26 };
27
28 ahb {
29 compatible = "simple-bus";
30 #address-cells = <1>;
31 #size-cells = <1>;
Wenyou Yang4529ee32017-03-23 14:26:23 +080032 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +080033
34 usb1: ohci@00400000 {
35 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
36 reg = <0x00400000 0x100000>;
37 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
38 clock-names = "ohci_clk", "hclk", "uhpck";
39 status = "disabled";
40 };
41
42 usb2: ehci@00500000 {
43 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
44 reg = <0x00500000 0x100000>;
45 clocks = <&utmi>, <&uhphs_clk>;
46 clock-names = "usb_clk", "ehci_clk";
47 status = "disabled";
48 };
49
50 sdmmc0: sdio-host@a0000000 {
51 compatible = "atmel,sama5d2-sdhci";
52 reg = <0xa0000000 0x300>;
53 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
54 clock-names = "hclock", "multclk", "baseclk";
55 status = "disabled";
56 };
57
58 sdmmc1: sdio-host@b0000000 {
59 compatible = "atmel,sama5d2-sdhci";
60 reg = <0xb0000000 0x300>;
61 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
62 clock-names = "hclock", "multclk", "baseclk";
63 status = "disabled";
64 };
65
66 apb {
67 compatible = "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <1>;
Wenyou Yang4529ee32017-03-23 14:26:23 +080070 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +080071
Wenyou Yangd2cd09b2017-09-18 15:25:57 +080072 hlcdc: hlcdc@f0000000 {
73 compatible = "atmel,at91sam9x5-hlcdc";
74 reg = <0xf0000000 0x2000>;
75 clocks = <&lcdc_clk>;
76 status = "disabled";
77 };
78
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +080079 pmc: pmc@f0014000 {
80 compatible = "atmel,sama5d2-pmc", "syscon";
81 reg = <0xf0014000 0x160>;
82 #address-cells = <1>;
83 #size-cells = <0>;
84 #interrupt-cells = <1>;
Wenyou Yang4529ee32017-03-23 14:26:23 +080085 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +080086
87 main: mainck {
88 compatible = "atmel,at91sam9x5-clk-main";
89 #clock-cells = <0>;
Wenyou Yang4529ee32017-03-23 14:26:23 +080090 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +080091 };
92
Wenyou Yang9e63c492016-09-18 15:37:47 +080093 plla: pllack@0 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +080094 compatible = "atmel,sama5d3-clk-pll";
95 #clock-cells = <0>;
96 clocks = <&main>;
97 reg = <0>;
98 atmel,clk-input-range = <12000000 12000000>;
99 #atmel,pll-clk-output-range-cells = <4>;
100 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800101 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800102 };
103
104 plladiv: plladivck {
105 compatible = "atmel,at91sam9x5-clk-plldiv";
106 #clock-cells = <0>;
107 clocks = <&plla>;
108 };
109
110 audio_pll_frac: audiopll_fracck {
111 compatible = "atmel,sama5d2-clk-audio-pll-frac";
112 #clock-cells = <0>;
113 clocks = <&main>;
114 };
115
116 audio_pll_pad: audiopll_padck {
117 compatible = "atmel,sama5d2-clk-audio-pll-pad";
118 #clock-cells = <0>;
119 clocks = <&audio_pll_frac>;
120 };
121
122 audio_pll_pmc: audiopll_pmcck {
123 compatible = "atmel,sama5d2-clk-audio-pll-pmc";
124 #clock-cells = <0>;
125 clocks = <&audio_pll_frac>;
126 };
127
128 utmi: utmick {
129 compatible = "atmel,at91sam9x5-clk-utmi";
130 #clock-cells = <0>;
131 clocks = <&main>;
Wenyou Yang56246d12017-09-05 18:30:08 +0800132 regmap-sfr = <&sfr>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800133 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800134 };
135
136 mck: masterck {
137 compatible = "atmel,at91sam9x5-clk-master";
138 #clock-cells = <0>;
139 clocks = <&main>, <&plladiv>, <&utmi>;
140 atmel,clk-output-range = <124000000 166000000>;
141 atmel,clk-divisors = <1 2 4 3>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800142 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800143 };
144
145 h32ck: h32mxck {
146 #clock-cells = <0>;
147 compatible = "atmel,sama5d4-clk-h32mx";
148 clocks = <&mck>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800149 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800150 };
151
152 usb: usbck {
153 compatible = "atmel,at91sam9x5-clk-usb";
154 #clock-cells = <0>;
155 clocks = <&plladiv>, <&utmi>;
156 };
157
158 prog: progck {
159 compatible = "atmel,at91sam9x5-clk-programmable";
160 #address-cells = <1>;
161 #size-cells = <0>;
162 interrupt-parent = <&pmc>;
163 clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
164
Wenyou Yang9e63c492016-09-18 15:37:47 +0800165 prog0: prog@0 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800166 #clock-cells = <0>;
167 reg = <0>;
168 };
169
Wenyou Yang9e63c492016-09-18 15:37:47 +0800170 prog1: prog@1 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800171 #clock-cells = <0>;
172 reg = <1>;
173 };
174
Wenyou Yang9e63c492016-09-18 15:37:47 +0800175 prog2: prog@2 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800176 #clock-cells = <0>;
177 reg = <2>;
178 };
179 };
180
181 systemck {
182 compatible = "atmel,at91rm9200-clk-system";
183 #address-cells = <1>;
184 #size-cells = <0>;
185
Wenyou Yang9e63c492016-09-18 15:37:47 +0800186 ddrck: ddrck@2 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800187 #clock-cells = <0>;
188 reg = <2>;
189 clocks = <&mck>;
190 };
191
Wenyou Yang9e63c492016-09-18 15:37:47 +0800192 lcdck: lcdck@3 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800193 #clock-cells = <0>;
194 reg = <3>;
195 clocks = <&mck>;
196 };
197
Wenyou Yang9e63c492016-09-18 15:37:47 +0800198 uhpck: uhpck@6 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800199 #clock-cells = <0>;
200 reg = <6>;
201 clocks = <&usb>;
202 };
203
Wenyou Yang9e63c492016-09-18 15:37:47 +0800204 udpck: udpck@7 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800205 #clock-cells = <0>;
206 reg = <7>;
207 clocks = <&usb>;
208 };
209
Wenyou Yang9e63c492016-09-18 15:37:47 +0800210 pck0: pck0@8 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800211 #clock-cells = <0>;
212 reg = <8>;
213 clocks = <&prog0>;
214 };
215
Wenyou Yang9e63c492016-09-18 15:37:47 +0800216 pck1: pck1@9 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800217 #clock-cells = <0>;
218 reg = <9>;
219 clocks = <&prog1>;
220 };
221
Wenyou Yang9e63c492016-09-18 15:37:47 +0800222 pck2: pck2@10 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800223 #clock-cells = <0>;
224 reg = <10>;
225 clocks = <&prog2>;
226 };
227
Wenyou Yang9e63c492016-09-18 15:37:47 +0800228 iscck: iscck@18 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800229 #clock-cells = <0>;
230 reg = <18>;
231 clocks = <&mck>;
232 };
233 };
234
235 periph32ck {
236 compatible = "atmel,at91sam9x5-clk-peripheral";
237 #address-cells = <1>;
238 #size-cells = <0>;
239 clocks = <&h32ck>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800240 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800241
Wenyou Yang9e63c492016-09-18 15:37:47 +0800242 macb0_clk: macb0_clk@5 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800243 #clock-cells = <0>;
244 reg = <5>;
245 atmel,clk-output-range = <0 83000000>;
246 };
247
Wenyou Yang9e63c492016-09-18 15:37:47 +0800248 tdes_clk: tdes_clk@11 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800249 #clock-cells = <0>;
250 reg = <11>;
251 atmel,clk-output-range = <0 83000000>;
252 };
253
Wenyou Yang9e63c492016-09-18 15:37:47 +0800254 matrix1_clk: matrix1_clk@14 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800255 #clock-cells = <0>;
256 reg = <14>;
257 };
258
Wenyou Yang9e63c492016-09-18 15:37:47 +0800259 hsmc_clk: hsmc_clk@17 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800260 #clock-cells = <0>;
261 reg = <17>;
262 };
263
Wenyou Yang9e63c492016-09-18 15:37:47 +0800264 pioA_clk: pioA_clk@18 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800265 #clock-cells = <0>;
266 reg = <18>;
267 atmel,clk-output-range = <0 83000000>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800268 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800269 };
270
Wenyou Yang9e63c492016-09-18 15:37:47 +0800271 flx0_clk: flx0_clk@19 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800272 #clock-cells = <0>;
273 reg = <19>;
274 atmel,clk-output-range = <0 83000000>;
275 };
276
Wenyou Yang9e63c492016-09-18 15:37:47 +0800277 flx1_clk: flx1_clk@20 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800278 #clock-cells = <0>;
279 reg = <20>;
280 atmel,clk-output-range = <0 83000000>;
281 };
282
Wenyou Yang9e63c492016-09-18 15:37:47 +0800283 flx2_clk: flx2_clk@21 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800284 #clock-cells = <0>;
285 reg = <21>;
286 atmel,clk-output-range = <0 83000000>;
287 };
288
Wenyou Yang9e63c492016-09-18 15:37:47 +0800289 flx3_clk: flx3_clk@22 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800290 #clock-cells = <0>;
291 reg = <22>;
292 atmel,clk-output-range = <0 83000000>;
293 };
294
Wenyou Yang9e63c492016-09-18 15:37:47 +0800295 flx4_clk: flx4_clk@23 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800296 #clock-cells = <0>;
297 reg = <23>;
298 atmel,clk-output-range = <0 83000000>;
299 };
300
Wenyou Yang9e63c492016-09-18 15:37:47 +0800301 uart0_clk: uart0_clk@24 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800302 #clock-cells = <0>;
303 reg = <24>;
304 atmel,clk-output-range = <0 83000000>;
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +0800305 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800306 };
307
Wenyou Yang9e63c492016-09-18 15:37:47 +0800308 uart1_clk: uart1_clk@25 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800309 #clock-cells = <0>;
310 reg = <25>;
311 atmel,clk-output-range = <0 83000000>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800312 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800313 };
314
Wenyou Yang9e63c492016-09-18 15:37:47 +0800315 uart2_clk: uart2_clk@26 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800316 #clock-cells = <0>;
317 reg = <26>;
318 atmel,clk-output-range = <0 83000000>;
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +0800319 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800320 };
321
Wenyou Yang9e63c492016-09-18 15:37:47 +0800322 uart3_clk: uart3_clk@27 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800323 #clock-cells = <0>;
324 reg = <27>;
325 atmel,clk-output-range = <0 83000000>;
326 };
327
Wenyou Yang9e63c492016-09-18 15:37:47 +0800328 uart4_clk: uart4_clk@28 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800329 #clock-cells = <0>;
330 reg = <28>;
331 atmel,clk-output-range = <0 83000000>;
332 };
333
Wenyou Yang9e63c492016-09-18 15:37:47 +0800334 twi0_clk: twi0_clk@29 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800335 reg = <29>;
336 #clock-cells = <0>;
337 atmel,clk-output-range = <0 83000000>;
338 };
339
Wenyou Yang9e63c492016-09-18 15:37:47 +0800340 twi1_clk: twi1_clk@30 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800341 #clock-cells = <0>;
342 reg = <30>;
343 atmel,clk-output-range = <0 83000000>;
344 };
345
Wenyou Yang9e63c492016-09-18 15:37:47 +0800346 spi0_clk: spi0_clk@33 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800347 #clock-cells = <0>;
348 reg = <33>;
349 atmel,clk-output-range = <0 83000000>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800350 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800351 };
352
Wenyou Yang9e63c492016-09-18 15:37:47 +0800353 spi1_clk: spi1_clk@34 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800354 #clock-cells = <0>;
355 reg = <34>;
356 atmel,clk-output-range = <0 83000000>;
357 };
358
Wenyou Yang9e63c492016-09-18 15:37:47 +0800359 tcb0_clk: tcb0_clk@35 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800360 #clock-cells = <0>;
361 reg = <35>;
362 atmel,clk-output-range = <0 83000000>;
363 };
364
Wenyou Yang9e63c492016-09-18 15:37:47 +0800365 tcb1_clk: tcb1_clk@36 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800366 #clock-cells = <0>;
367 reg = <36>;
368 atmel,clk-output-range = <0 83000000>;
369 };
370
Wenyou Yang9e63c492016-09-18 15:37:47 +0800371 pwm_clk: pwm_clk@38 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800372 #clock-cells = <0>;
373 reg = <38>;
374 atmel,clk-output-range = <0 83000000>;
375 };
376
Wenyou Yang9e63c492016-09-18 15:37:47 +0800377 adc_clk: adc_clk@40 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800378 #clock-cells = <0>;
379 reg = <40>;
380 atmel,clk-output-range = <0 83000000>;
381 };
382
Wenyou Yang9e63c492016-09-18 15:37:47 +0800383 uhphs_clk: uhphs_clk@41 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800384 #clock-cells = <0>;
385 reg = <41>;
386 atmel,clk-output-range = <0 83000000>;
387 };
388
Wenyou Yang9e63c492016-09-18 15:37:47 +0800389 udphs_clk: udphs_clk@42 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800390 #clock-cells = <0>;
391 reg = <42>;
392 atmel,clk-output-range = <0 83000000>;
393 };
394
Wenyou Yang9e63c492016-09-18 15:37:47 +0800395 ssc0_clk: ssc0_clk@43 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800396 #clock-cells = <0>;
397 reg = <43>;
398 atmel,clk-output-range = <0 83000000>;
399 };
400
Wenyou Yang9e63c492016-09-18 15:37:47 +0800401 ssc1_clk: ssc1_clk@44 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800402 #clock-cells = <0>;
403 reg = <44>;
404 atmel,clk-output-range = <0 83000000>;
405 };
406
Wenyou Yang9e63c492016-09-18 15:37:47 +0800407 trng_clk: trng_clk@47 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800408 #clock-cells = <0>;
409 reg = <47>;
410 atmel,clk-output-range = <0 83000000>;
411 };
412
Wenyou Yang9e63c492016-09-18 15:37:47 +0800413 pdmic_clk: pdmic_clk@48 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800414 #clock-cells = <0>;
415 reg = <48>;
416 atmel,clk-output-range = <0 83000000>;
417 };
418
Wenyou Yang9e63c492016-09-18 15:37:47 +0800419 i2s0_clk: i2s0_clk@54 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800420 #clock-cells = <0>;
421 reg = <54>;
422 atmel,clk-output-range = <0 83000000>;
423 };
424
Wenyou Yang9e63c492016-09-18 15:37:47 +0800425 i2s1_clk: i2s1_clk@55 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800426 #clock-cells = <0>;
427 reg = <55>;
428 atmel,clk-output-range = <0 83000000>;
429 };
430
Wenyou Yang9e63c492016-09-18 15:37:47 +0800431 can0_clk: can0_clk@56 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800432 #clock-cells = <0>;
433 reg = <56>;
434 atmel,clk-output-range = <0 83000000>;
435 };
436
Wenyou Yang9e63c492016-09-18 15:37:47 +0800437 can1_clk: can1_clk@57 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800438 #clock-cells = <0>;
439 reg = <57>;
440 atmel,clk-output-range = <0 83000000>;
441 };
442
Wenyou Yang9e63c492016-09-18 15:37:47 +0800443 classd_clk: classd_clk@59 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800444 #clock-cells = <0>;
445 reg = <59>;
446 atmel,clk-output-range = <0 83000000>;
447 };
448 };
449
450 periph64ck {
451 compatible = "atmel,at91sam9x5-clk-peripheral";
452 #address-cells = <1>;
453 #size-cells = <0>;
454 clocks = <&mck>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800455 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800456
Wenyou Yang9e63c492016-09-18 15:37:47 +0800457 dma0_clk: dma0_clk@6 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800458 #clock-cells = <0>;
459 reg = <6>;
460 };
461
Wenyou Yang9e63c492016-09-18 15:37:47 +0800462 dma1_clk: dma1_clk@7 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800463 #clock-cells = <0>;
464 reg = <7>;
465 };
466
Wenyou Yang9e63c492016-09-18 15:37:47 +0800467 aes_clk: aes_clk@9 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800468 #clock-cells = <0>;
469 reg = <9>;
470 };
471
Wenyou Yang9e63c492016-09-18 15:37:47 +0800472 aesb_clk: aesb_clk@10 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800473 #clock-cells = <0>;
474 reg = <10>;
475 };
476
Wenyou Yang9e63c492016-09-18 15:37:47 +0800477 sha_clk: sha_clk@12 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800478 #clock-cells = <0>;
479 reg = <12>;
480 };
481
Wenyou Yang9e63c492016-09-18 15:37:47 +0800482 mpddr_clk: mpddr_clk@13 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800483 #clock-cells = <0>;
484 reg = <13>;
485 };
486
Wenyou Yang9e63c492016-09-18 15:37:47 +0800487 matrix0_clk: matrix0_clk@15 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800488 #clock-cells = <0>;
489 reg = <15>;
490 };
491
Wenyou Yang9e63c492016-09-18 15:37:47 +0800492 sdmmc0_hclk: sdmmc0_hclk@31 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800493 #clock-cells = <0>;
494 reg = <31>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800495 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800496 };
497
Wenyou Yang9e63c492016-09-18 15:37:47 +0800498 sdmmc1_hclk: sdmmc1_hclk@32 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800499 #clock-cells = <0>;
500 reg = <32>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800501 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800502 };
503
Wenyou Yang9e63c492016-09-18 15:37:47 +0800504 lcdc_clk: lcdc_clk@45 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800505 #clock-cells = <0>;
506 reg = <45>;
507 };
508
Wenyou Yang9e63c492016-09-18 15:37:47 +0800509 isc_clk: isc_clk@46 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800510 #clock-cells = <0>;
511 reg = <46>;
512 };
513
Wenyou Yang9e63c492016-09-18 15:37:47 +0800514 qspi0_clk: qspi0_clk@52 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800515 #clock-cells = <0>;
516 reg = <52>;
Wenyou Yangce4054b2017-09-13 14:58:54 +0800517 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800518 };
519
Wenyou Yang9e63c492016-09-18 15:37:47 +0800520 qspi1_clk: qspi1_clk@53 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800521 #clock-cells = <0>;
522 reg = <53>;
Wenyou Yangce4054b2017-09-13 14:58:54 +0800523 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800524 };
525 };
526
527 gck {
528 compatible = "atmel,sama5d2-clk-generated";
529 #address-cells = <1>;
530 #size-cells = <0>;
531 interrupt-parent = <&pmc>;
532 clocks = <&main>, <&plla>, <&utmi>, <&mck>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800533 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800534
Wenyou Yang9e63c492016-09-18 15:37:47 +0800535 sdmmc0_gclk: sdmmc0_gclk@31 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800536 #clock-cells = <0>;
537 reg = <31>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800538 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800539 };
540
Wenyou Yang9e63c492016-09-18 15:37:47 +0800541 sdmmc1_gclk: sdmmc1_gclk@32 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800542 #clock-cells = <0>;
543 reg = <32>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800544 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800545 };
546
Wenyou Yang9e63c492016-09-18 15:37:47 +0800547 tcb0_gclk: tcb0_gclk@35 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800548 #clock-cells = <0>;
549 reg = <35>;
550 atmel,clk-output-range = <0 83000000>;
551 };
552
Wenyou Yang9e63c492016-09-18 15:37:47 +0800553 tcb1_gclk: tcb1_gclk@36 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800554 #clock-cells = <0>;
555 reg = <36>;
556 atmel,clk-output-range = <0 83000000>;
557 };
558
Wenyou Yang9e63c492016-09-18 15:37:47 +0800559 pwm_gclk: pwm_gclk@38 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800560 #clock-cells = <0>;
561 reg = <38>;
562 atmel,clk-output-range = <0 83000000>;
563 };
564
Wenyou Yang9e63c492016-09-18 15:37:47 +0800565 pdmic_gclk: pdmic_gclk@48 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800566 #clock-cells = <0>;
567 reg = <48>;
568 };
569
Wenyou Yang9e63c492016-09-18 15:37:47 +0800570 i2s0_gclk: i2s0_gclk@54 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800571 #clock-cells = <0>;
572 reg = <54>;
573 };
574
Wenyou Yang9e63c492016-09-18 15:37:47 +0800575 i2s1_gclk: i2s1_gclk@55 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800576 #clock-cells = <0>;
577 reg = <55>;
578 };
579
Wenyou Yang9e63c492016-09-18 15:37:47 +0800580 can0_gclk: can0_gclk@56 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800581 #clock-cells = <0>;
582 reg = <56>;
583 atmel,clk-output-range = <0 80000000>;
584 };
585
Wenyou Yang9e63c492016-09-18 15:37:47 +0800586 can1_gclk: can1_gclk@57 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800587 #clock-cells = <0>;
588 reg = <57>;
589 atmel,clk-output-range = <0 80000000>;
590 };
591
Wenyou Yang9e63c492016-09-18 15:37:47 +0800592 classd_gclk: classd_gclk@59 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800593 #clock-cells = <0>;
594 reg = <59>;
595 atmel,clk-output-range = <0 100000000>;
596 };
597 };
598 };
599
600 qspi0: spi@f0020000 {
601 compatible = "atmel,sama5d2-qspi";
602 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
603 reg-names = "qspi_base", "qspi_mmap";
604 #address-cells = <1>;
605 #size-cells = <0>;
606 clocks = <&qspi0_clk>;
607 status = "disabled";
608 };
609
Wenyou Yangce4054b2017-09-13 14:58:54 +0800610 qspi1: spi@f0024000 {
611 compatible = "atmel,sama5d2-qspi";
612 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
613 reg-names = "qspi_base", "qspi_mmap";
614 #address-cells = <1>;
615 #size-cells = <0>;
616 clocks = <&qspi1_clk>;
617 status = "disabled";
618 };
619
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800620 spi0: spi@f8000000 {
621 compatible = "atmel,at91rm9200-spi";
622 reg = <0xf8000000 0x100>;
623 clocks = <&spi0_clk>;
624 clock-names = "spi_clk";
625 #address-cells = <1>;
626 #size-cells = <0>;
627 status = "disabled";
628 };
629
630 macb0: ethernet@f8008000 {
631 compatible = "cdns,macb";
632 reg = <0xf8008000 0x1000>;
633 #address-cells = <1>;
634 #size-cells = <0>;
635 clocks = <&macb0_clk>, <&macb0_clk>;
636 clock-names = "hclk", "pclk";
637 status = "disabled";
638 };
639
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +0800640 uart0: serial@f801c000 {
641 compatible = "atmel,at91sam9260-usart";
642 reg = <0xf801c000 0x100>;
643 clocks = <&uart0_clk>;
644 clock-names = "usart";
645 status = "disabled";
646 };
647
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800648 uart1: serial@f8020000 {
649 compatible = "atmel,at91sam9260-usart";
650 reg = <0xf8020000 0x100>;
Wenyou Yang20bb1652017-03-23 14:26:22 +0800651 clocks = <&uart1_clk>;
652 clock-names = "usart";
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800653 status = "disabled";
654 };
655
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +0800656 uart2: serial@f8024000 {
657 compatible = "atmel,at91sam9260-usart";
658 reg = <0xf8024000 0x100>;
659 clocks = <&uart2_clk>;
660 clock-names = "usart";
661 status = "disabled";
662 };
663
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800664 i2c0: i2c@f8028000 {
665 compatible = "atmel,sama5d2-i2c";
666 reg = <0xf8028000 0x100>;
667 #address-cells = <1>;
668 #size-cells = <0>;
669 clocks = <&twi0_clk>;
670 status = "disabled";
671 };
672
Wenyou.Yang@microchip.comfc6adeb2017-08-15 17:40:27 +0800673 rstc@f8048000 {
674 compatible = "atmel,sama5d3-rstc";
675 reg = <0xf8048000 0x10>;
676 clocks = <&clk32k>;
677 };
678
679 shdwc@f8048010 {
680 compatible = "atmel,sama5d2-shdwc";
681 reg = <0xf8048010 0x10>;
682 clocks = <&clk32k>;
683 #address-cells = <1>;
684 #size-cells = <0>;
685 atmel,wakeup-rtc-timer;
686 };
687
688 pit: timer@f8048030 {
689 compatible = "atmel,at91sam9260-pit";
690 reg = <0xf8048030 0x10>;
691 clocks = <&h32ck>;
692 };
693
694 watchdog@f8048040 {
695 compatible = "atmel,sama5d4-wdt";
696 reg = <0xf8048040 0x10>;
697 clocks = <&clk32k>;
698 status = "disabled";
699 };
700
Wenyou Yang56246d12017-09-05 18:30:08 +0800701 sfr: sfr@f8030000 {
702 compatible = "atmel,sama5d2-sfr", "syscon";
703 reg = <0xf8030000 0x98>;
704 };
705
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800706 sckc@f8048050 {
707 compatible = "atmel,at91sam9x5-sckc";
708 reg = <0xf8048050 0x4>;
709
710 slow_rc_osc: slow_rc_osc {
711 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
712 #clock-cells = <0>;
713 clock-frequency = <32768>;
714 clock-accuracy = <250000000>;
715 atmel,startup-time-usec = <75>;
716 };
717
718 slow_osc: slow_osc {
719 compatible = "atmel,at91sam9x5-clk-slow-osc";
720 #clock-cells = <0>;
721 clocks = <&slow_xtal>;
722 atmel,startup-time-usec = <1200000>;
723 };
724
725 clk32k: slowck {
726 compatible = "atmel,at91sam9x5-clk-slow";
727 #clock-cells = <0>;
728 clocks = <&slow_rc_osc &slow_osc>;
729 };
730 };
731
732 spi1: spi@fc000000 {
733 compatible = "atmel,at91rm9200-spi";
734 reg = <0xfc000000 0x100>;
735 #address-cells = <1>;
736 #size-cells = <0>;
737 status = "disabled";
738 };
739
Wenyou Yangce4054b2017-09-13 14:58:54 +0800740 uart3: serial@fc008000 {
741 compatible = "atmel,at91sam9260-usart";
742 reg = <0xfc008000 0x100>;
743 clocks = <&uart3_clk>;
744 clock-names = "usart";
745 status = "disabled";
746 };
747
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800748 i2c1: i2c@fc028000 {
749 compatible = "atmel,sama5d2-i2c";
750 reg = <0xfc028000 0x100>;
751 #address-cells = <1>;
752 #size-cells = <0>;
753 clocks = <&twi1_clk>;
754 status = "disabled";
755 };
756
757 pioA: gpio@fc038000 {
758 compatible = "atmel,sama5d2-gpio";
759 reg = <0xfc038000 0x600>;
760 clocks = <&pioA_clk>;
761 gpio-controller;
762 #gpio-cells = <2>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800763 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800764
765 pinctrl {
766 compatible = "atmel,sama5d2-pinctrl";
Wenyou Yang4529ee32017-03-23 14:26:23 +0800767 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800768 };
769 };
770 };
771 };
Eugen Hristev7f0110d2018-09-18 10:35:53 +0300772
773 onewire_tm: onewire {
774 compatible = "w1-gpio";
775 status = "disabled";
776 };
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800777};