Marek Vasut | b52fb0b | 2020-04-29 20:09:08 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2018 Wandboard, Org. |
| 4 | * Copyright 2017 NXP |
| 5 | * |
| 6 | * Author: Richard Hu <hakahu@gmail.com> |
| 7 | */ |
| 8 | |
| 9 | /dts-v1/; |
| 10 | |
| 11 | #include "imx8mq.dtsi" |
Peng Fan | ddc890b | 2021-10-22 10:42:18 +0800 | [diff] [blame] | 12 | #include "imx8mq-u-boot.dtsi" |
Marek Vasut | b52fb0b | 2020-04-29 20:09:08 +0200 | [diff] [blame] | 13 | |
| 14 | / { |
| 15 | model = "TechNexion PICO-PI-8M"; |
| 16 | compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq"; |
| 17 | |
| 18 | chosen { |
| 19 | stdout-path = &uart1; |
| 20 | }; |
| 21 | |
| 22 | pmic_osc: clock-pmic { |
| 23 | compatible = "fixed-clock"; |
| 24 | #clock-cells = <0>; |
| 25 | clock-frequency = <32768>; |
| 26 | clock-output-names = "pmic_osc"; |
| 27 | }; |
| 28 | |
| 29 | reg_usb_otg_vbus: regulator-usb-otg-vbus { |
| 30 | pinctrl-names = "default"; |
| 31 | pinctrl-0 = <&pinctrl_otg_vbus>; |
| 32 | compatible = "regulator-fixed"; |
| 33 | regulator-name = "usb_otg_vbus"; |
| 34 | regulator-min-microvolt = <5000000>; |
| 35 | regulator-max-microvolt = <5000000>; |
| 36 | gpio = <&gpio3 14 GPIO_ACTIVE_LOW>; |
| 37 | }; |
| 38 | |
| 39 | reg_eth_phy: eth_phy { |
| 40 | compatible = "regulator-fixed"; |
| 41 | regulator-name = "eth_phy_pwr"; |
| 42 | regulator-min-microvolt = <3300000>; |
| 43 | regulator-max-microvolt = <3300000>; |
| 44 | gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; |
| 45 | }; |
| 46 | }; |
| 47 | |
| 48 | &fec1 { |
| 49 | pinctrl-names = "default"; |
| 50 | pinctrl-0 = <&pinctrl_fec1>; |
| 51 | phy-mode = "rgmii-id"; |
| 52 | phy-handle = <ðphy0>; |
| 53 | phy-supply = <®_eth_phy>; |
| 54 | phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; |
| 55 | phy-reset-duration = <100>; |
| 56 | phy-reset-post-delay = <100>; |
| 57 | fsl,magic-packet; |
| 58 | status = "okay"; |
| 59 | |
| 60 | mdio { |
| 61 | #address-cells = <1>; |
| 62 | #size-cells = <0>; |
| 63 | |
| 64 | ethphy0: ethernet-phy@1 { |
| 65 | compatible = "ethernet-phy-ieee802.3-c22"; |
| 66 | reg = <1>; |
| 67 | }; |
| 68 | }; |
| 69 | }; |
| 70 | |
| 71 | &i2c1 { |
| 72 | clock-frequency = <100000>; |
| 73 | pinctrl-names = "default"; |
| 74 | pinctrl-0 = <&pinctrl_i2c1>; |
| 75 | status = "okay"; |
| 76 | |
| 77 | pmic: pmic@4b { |
| 78 | reg = <0x4b>; |
| 79 | compatible = "rohm,bd71837"; |
| 80 | pinctrl-names = "default"; |
| 81 | pinctrl-0 = <&pinctrl_pmic>; |
| 82 | clocks = <&pmic_osc>; |
| 83 | clock-names = "osc"; |
| 84 | clock-output-names = "pmic_clk"; |
| 85 | interrupt-parent = <&gpio1>; |
| 86 | interrupts = <3 GPIO_ACTIVE_LOW>; |
| 87 | interrupt-names = "irq"; |
| 88 | |
| 89 | regulators { |
| 90 | buck1: BUCK1 { |
| 91 | regulator-name = "buck1"; |
| 92 | regulator-min-microvolt = <700000>; |
| 93 | regulator-max-microvolt = <1300000>; |
| 94 | regulator-boot-on; |
| 95 | regulator-ramp-delay = <1250>; |
| 96 | rohm,dvs-run-voltage = <900000>; |
| 97 | rohm,dvs-idle-voltage = <850000>; |
| 98 | rohm,dvs-suspend-voltage = <800000>; |
| 99 | }; |
| 100 | |
| 101 | buck2: BUCK2 { |
| 102 | regulator-name = "buck2"; |
| 103 | regulator-min-microvolt = <700000>; |
| 104 | regulator-max-microvolt = <1300000>; |
| 105 | regulator-boot-on; |
| 106 | regulator-ramp-delay = <1250>; |
| 107 | rohm,dvs-run-voltage = <1000000>; |
| 108 | rohm,dvs-idle-voltage = <900000>; |
| 109 | }; |
| 110 | |
| 111 | buck3: BUCK3 { |
| 112 | regulator-name = "buck3"; |
| 113 | regulator-min-microvolt = <700000>; |
| 114 | regulator-max-microvolt = <1300000>; |
| 115 | regulator-boot-on; |
| 116 | rohm,dvs-run-voltage = <1000000>; |
| 117 | }; |
| 118 | |
| 119 | buck4: BUCK4 { |
| 120 | regulator-name = "buck4"; |
| 121 | regulator-min-microvolt = <700000>; |
| 122 | regulator-max-microvolt = <1300000>; |
| 123 | regulator-boot-on; |
| 124 | rohm,dvs-run-voltage = <1000000>; |
| 125 | }; |
| 126 | |
| 127 | buck5: BUCK5 { |
| 128 | regulator-name = "buck5"; |
| 129 | regulator-min-microvolt = <700000>; |
| 130 | regulator-max-microvolt = <1350000>; |
| 131 | regulator-boot-on; |
| 132 | }; |
| 133 | |
| 134 | buck6: BUCK6 { |
| 135 | regulator-name = "buck6"; |
| 136 | regulator-min-microvolt = <3000000>; |
| 137 | regulator-max-microvolt = <3300000>; |
| 138 | regulator-boot-on; |
| 139 | }; |
| 140 | |
| 141 | buck7: BUCK7 { |
| 142 | regulator-name = "buck7"; |
| 143 | regulator-min-microvolt = <1605000>; |
| 144 | regulator-max-microvolt = <1995000>; |
| 145 | regulator-boot-on; |
| 146 | }; |
| 147 | |
| 148 | buck8: BUCK8 { |
| 149 | regulator-name = "buck8"; |
| 150 | regulator-min-microvolt = <800000>; |
| 151 | regulator-max-microvolt = <1400000>; |
| 152 | regulator-boot-on; |
| 153 | }; |
| 154 | |
| 155 | ldo1: LDO1 { |
| 156 | regulator-name = "ldo1"; |
| 157 | regulator-min-microvolt = <3000000>; |
| 158 | regulator-max-microvolt = <3300000>; |
| 159 | regulator-boot-on; |
| 160 | regulator-always-on; |
| 161 | }; |
| 162 | |
| 163 | ldo2: LDO2 { |
| 164 | regulator-name = "ldo2"; |
| 165 | regulator-min-microvolt = <900000>; |
| 166 | regulator-max-microvolt = <900000>; |
| 167 | regulator-boot-on; |
| 168 | regulator-always-on; |
| 169 | }; |
| 170 | |
| 171 | ldo3: LDO3 { |
| 172 | regulator-name = "ldo3"; |
| 173 | regulator-min-microvolt = <1800000>; |
| 174 | regulator-max-microvolt = <3300000>; |
| 175 | regulator-boot-on; |
| 176 | }; |
| 177 | |
| 178 | ldo4: LDO4 { |
| 179 | regulator-name = "ldo4"; |
| 180 | regulator-min-microvolt = <900000>; |
| 181 | regulator-max-microvolt = <1800000>; |
| 182 | regulator-boot-on; |
| 183 | }; |
| 184 | |
| 185 | ldo5: LDO5 { |
| 186 | regulator-name = "ldo5"; |
| 187 | regulator-min-microvolt = <1800000>; |
| 188 | regulator-max-microvolt = <3300000>; |
| 189 | regulator-boot-on; |
| 190 | }; |
| 191 | |
| 192 | ldo6: LDO6 { |
| 193 | regulator-name = "ldo6"; |
| 194 | regulator-min-microvolt = <900000>; |
| 195 | regulator-max-microvolt = <1800000>; |
| 196 | regulator-boot-on; |
| 197 | }; |
| 198 | |
| 199 | ldo7: LDO7 { |
| 200 | regulator-name = "ldo7"; |
| 201 | regulator-min-microvolt = <1800000>; |
| 202 | regulator-max-microvolt = <3300000>; |
| 203 | regulator-boot-on; |
| 204 | }; |
| 205 | }; |
| 206 | }; |
| 207 | }; |
| 208 | |
| 209 | &i2c2 { |
| 210 | clock-frequency = <100000>; |
| 211 | pinctrl-names = "default"; |
| 212 | pinctrl-0 = <&pinctrl_i2c2>; |
| 213 | status = "okay"; |
| 214 | }; |
| 215 | |
| 216 | &uart1 { /* console */ |
| 217 | pinctrl-names = "default"; |
| 218 | pinctrl-0 = <&pinctrl_uart1>; |
| 219 | status = "okay"; |
| 220 | }; |
| 221 | |
| 222 | &usdhc1 { |
| 223 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| 224 | pinctrl-0 = <&pinctrl_usdhc1>; |
| 225 | pinctrl-1 = <&pinctrl_usdhc1_100mhz>; |
| 226 | pinctrl-2 = <&pinctrl_usdhc1_200mhz>; |
| 227 | bus-width = <8>; |
| 228 | non-removable; |
| 229 | status = "okay"; |
| 230 | }; |
| 231 | |
| 232 | &usdhc2 { |
| 233 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| 234 | pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| 235 | pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; |
| 236 | pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; |
| 237 | bus-width = <4>; |
| 238 | cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; |
| 239 | status = "okay"; |
| 240 | }; |
| 241 | |
| 242 | &usb3_phy0 { |
| 243 | status = "okay"; |
| 244 | }; |
| 245 | |
| 246 | &usb3_phy1 { |
| 247 | status = "okay"; |
| 248 | }; |
| 249 | |
| 250 | &usb_dwc3_1 { |
| 251 | dr_mode = "host"; |
| 252 | status = "okay"; |
| 253 | }; |
| 254 | |
| 255 | &wdog1 { |
| 256 | pinctrl-names = "default"; |
| 257 | pinctrl-0 = <&pinctrl_wdog>; |
| 258 | fsl,ext-reset-output; |
| 259 | status = "okay"; |
| 260 | }; |
| 261 | |
| 262 | &iomuxc { |
| 263 | pinctrl_fec1: fec1grp { |
| 264 | fsl,pins = < |
| 265 | MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 |
| 266 | MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 |
| 267 | MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f |
| 268 | MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f |
| 269 | MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f |
| 270 | MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f |
| 271 | MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 |
| 272 | MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 |
| 273 | MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 |
| 274 | MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 |
| 275 | MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f |
| 276 | MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 |
| 277 | MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 |
| 278 | MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f |
| 279 | MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19 |
| 280 | MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 |
| 281 | >; |
| 282 | }; |
| 283 | |
| 284 | pinctrl_i2c1: i2c1grp { |
| 285 | fsl,pins = < |
| 286 | MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f |
| 287 | MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f |
| 288 | >; |
| 289 | }; |
| 290 | |
| 291 | pinctrl_i2c2: i2c2grp { |
| 292 | fsl,pins = < |
| 293 | MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f |
| 294 | MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f |
| 295 | >; |
| 296 | }; |
| 297 | |
| 298 | pinctrl_otg_vbus: otgvbusgrp { |
| 299 | fsl,pins = < |
| 300 | MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */ |
| 301 | >; |
| 302 | }; |
| 303 | |
| 304 | pinctrl_pmic: pmicirq { |
| 305 | fsl,pins = < |
| 306 | MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 |
| 307 | >; |
| 308 | }; |
| 309 | |
| 310 | pinctrl_uart1: uart1grp { |
| 311 | fsl,pins = < |
| 312 | MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 |
| 313 | MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 |
| 314 | >; |
| 315 | }; |
| 316 | |
| 317 | pinctrl_uart2: uart2grp { |
| 318 | fsl,pins = < |
| 319 | MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 |
| 320 | MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 |
| 321 | MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 |
| 322 | MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 |
| 323 | >; |
| 324 | }; |
| 325 | |
| 326 | pinctrl_usdhc1: usdhc1grp { |
| 327 | fsl,pins = < |
| 328 | MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 |
| 329 | MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 |
| 330 | MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 |
| 331 | MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 |
| 332 | MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 |
| 333 | MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 |
| 334 | MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 |
| 335 | MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 |
| 336 | MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 |
| 337 | MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 |
| 338 | MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 |
| 339 | >; |
| 340 | }; |
| 341 | |
| 342 | pinctrl_usdhc1_100mhz: usdhc1grp100mhz { |
| 343 | fsl,pins = < |
| 344 | MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 |
| 345 | MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 |
| 346 | MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 |
| 347 | MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 |
| 348 | MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 |
| 349 | MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 |
| 350 | MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 |
| 351 | MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 |
| 352 | MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 |
| 353 | MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 |
| 354 | MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 |
| 355 | >; |
| 356 | }; |
| 357 | |
| 358 | pinctrl_usdhc1_200mhz: usdhc1grp200mhz { |
| 359 | fsl,pins = < |
| 360 | MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 |
| 361 | MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 |
| 362 | MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 |
| 363 | MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 |
| 364 | MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 |
| 365 | MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 |
| 366 | MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 |
| 367 | MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 |
| 368 | MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 |
| 369 | MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 |
| 370 | MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 |
| 371 | >; |
| 372 | }; |
| 373 | |
| 374 | pinctrl_usdhc2_gpio: usdhc2grpgpio { |
| 375 | fsl,pins = < |
| 376 | MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 |
| 377 | >; |
| 378 | }; |
| 379 | |
| 380 | pinctrl_usdhc2: usdhc2grp { |
| 381 | fsl,pins = < |
| 382 | MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 |
| 383 | MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 |
| 384 | MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 |
| 385 | MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 |
| 386 | MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 |
| 387 | MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 |
| 388 | MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 |
| 389 | >; |
| 390 | }; |
| 391 | |
| 392 | pinctrl_usdhc2_100mhz: usdhc2grp100mhz { |
| 393 | fsl,pins = < |
| 394 | MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 |
| 395 | MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 |
| 396 | MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 |
| 397 | MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 |
| 398 | MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 |
| 399 | MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 |
| 400 | MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 |
| 401 | >; |
| 402 | }; |
| 403 | |
| 404 | pinctrl_usdhc2_200mhz: usdhc2grp200mhz { |
| 405 | fsl,pins = < |
| 406 | MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 |
| 407 | MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 |
| 408 | MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 |
| 409 | MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 |
| 410 | MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 |
| 411 | MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 |
| 412 | MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 |
| 413 | >; |
| 414 | }; |
| 415 | |
| 416 | pinctrl_wdog: wdoggrp { |
| 417 | fsl,pins = < |
| 418 | MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 |
| 419 | >; |
| 420 | }; |
| 421 | }; |