Michal Simek | 6ded73a | 2016-09-19 10:41:55 +0200 | [diff] [blame] | 1 | menu "FPGA support" |
| 2 | |
Siva Durga Prasad Paladugu | 6b24501 | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 3 | config FPGA |
| 4 | bool |
| 5 | |
Patrick Bruenn | 98d62e6 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 6 | config FPGA_ALTERA |
| 7 | bool "Enable Altera FPGA drivers" |
| 8 | select FPGA |
| 9 | help |
| 10 | Say Y here to enable the Altera FPGA driver |
| 11 | |
| 12 | This provides basic infrastructure to support Altera FPGA devices. |
| 13 | Enable Altera FPGA specific functions which includes bitstream |
| 14 | (in BIT format), fpga and device validation. |
| 15 | |
Tien Fong Chee | fa23ba1 | 2017-07-26 13:05:40 +0800 | [diff] [blame] | 16 | config FPGA_SOCFPGA |
| 17 | bool "Enable Gen5 and Arria10 common FPGA drivers" |
| 18 | select FPGA_ALTERA |
| 19 | help |
| 20 | Say Y here to enable the Gen5 and Arria10 common FPGA driver |
| 21 | |
| 22 | This provides common functionality for Gen5 and Arria10 devices. |
| 23 | |
Tom Rini | 6e52cb2 | 2022-06-12 20:02:00 -0400 | [diff] [blame] | 24 | config FPGA_STRATIX_V |
| 25 | bool "Enable Stratix V FPGA drivers" |
| 26 | depends on FPGA_ALTERA |
| 27 | help |
| 28 | Say Y here to enable the Altera Stratix V FPGA specific driver. |
| 29 | |
Patrick Bruenn | 98d62e6 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 30 | config FPGA_CYCLON2 |
| 31 | bool "Enable Altera FPGA driver for Cyclone II" |
| 32 | depends on FPGA_ALTERA |
| 33 | help |
| 34 | Say Y here to enable the Altera Cyclone II FPGA specific driver |
| 35 | |
| 36 | This provides common functionality for Altera Cyclone II devices. |
| 37 | Enable FPGA driver for loading bitstream in BIT and BIN format |
| 38 | on Altera Cyclone II device. |
| 39 | |
Chee Hong Ang | d217016 | 2020-08-07 11:50:03 +0800 | [diff] [blame] | 40 | config FPGA_INTEL_SDM_MAILBOX |
| 41 | bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver" |
Siew Chin Lim | 9a5bbdf | 2021-03-01 20:04:10 +0800 | [diff] [blame] | 42 | depends on TARGET_SOCFPGA_SOC64 |
Ang, Chee Hong | c41e660 | 2018-12-19 18:35:14 -0800 | [diff] [blame] | 43 | select FPGA_ALTERA |
| 44 | help |
Chee Hong Ang | d217016 | 2020-08-07 11:50:03 +0800 | [diff] [blame] | 45 | Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver |
Ang, Chee Hong | c41e660 | 2018-12-19 18:35:14 -0800 | [diff] [blame] | 46 | |
Chee Hong Ang | d217016 | 2020-08-07 11:50:03 +0800 | [diff] [blame] | 47 | This provides common functionality for Intel FPGA devices. |
| 48 | Enable FPGA driver for writing full bitstream into Intel FPGA |
| 49 | devices through SDM (Secure Device Manager) Mailbox. |
Ang, Chee Hong | c41e660 | 2018-12-19 18:35:14 -0800 | [diff] [blame] | 50 | |
Siva Durga Prasad Paladugu | 6b24501 | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 51 | config FPGA_XILINX |
| 52 | bool "Enable Xilinx FPGA drivers" |
| 53 | select FPGA |
| 54 | help |
| 55 | Enable Xilinx FPGA specific functions which includes bitstream |
| 56 | (in BIT format), fpga and device validation. |
| 57 | |
| 58 | config FPGA_ZYNQMPPL |
| 59 | bool "Enable Xilinx FPGA driver for ZynqMP" |
| 60 | depends on FPGA_XILINX |
| 61 | help |
| 62 | Enable FPGA driver for loading bitstream in BIT and BIN format |
| 63 | on Xilinx Zynq UltraScale+ (ZynqMP) device. |
| 64 | |
Siva Durga Prasad Paladugu | 26e054c | 2019-08-05 15:54:59 +0530 | [diff] [blame] | 65 | config FPGA_VERSALPL |
| 66 | bool "Enable Xilinx FPGA driver for Versal" |
| 67 | depends on FPGA_XILINX |
| 68 | help |
| 69 | Enable FPGA driver for loading bitstream in PDI format on Xilinx |
| 70 | Versal device. PDI is a new programmable device image format for |
| 71 | Versal. The bitstream will only be generated as PDI for Versal |
| 72 | platform. |
| 73 | |
Vipul Kumar | f415834 | 2018-02-16 18:02:49 +0530 | [diff] [blame] | 74 | config FPGA_SPARTAN3 |
Michal Simek | a225f81 | 2018-07-23 15:59:55 +0200 | [diff] [blame] | 75 | bool "Enable Spartan3 FPGA driver" |
Robert Hancock | 25d63a3 | 2019-06-18 09:47:13 -0600 | [diff] [blame] | 76 | depends on FPGA_XILINX |
Michal Simek | a225f81 | 2018-07-23 15:59:55 +0200 | [diff] [blame] | 77 | help |
| 78 | Enable Spartan3 FPGA driver for loading in BIT format. |
Vipul Kumar | f415834 | 2018-02-16 18:02:49 +0530 | [diff] [blame] | 79 | |
Robert Hancock | 25d63a3 | 2019-06-18 09:47:13 -0600 | [diff] [blame] | 80 | config FPGA_VIRTEX2 |
| 81 | bool "Enable Xilinx Virtex-II and later FPGA driver" |
| 82 | depends on FPGA_XILINX |
| 83 | help |
| 84 | Enable Virtex-II FPGA driver for loading in BIT format. This driver |
| 85 | also supports many newer Xilinx FPGA families. |
| 86 | |
Vipul Kumar | 3990c9d | 2018-02-16 18:02:51 +0530 | [diff] [blame] | 87 | config FPGA_ZYNQPL |
Michal Simek | a225f81 | 2018-07-23 15:59:55 +0200 | [diff] [blame] | 88 | bool "Enable Xilinx FPGA for Zynq" |
| 89 | depends on ARCH_ZYNQ |
| 90 | help |
| 91 | Enable FPGA driver for loading bitstream in BIT and BIN format |
| 92 | on Xilinx Zynq devices. |
Vipul Kumar | 3990c9d | 2018-02-16 18:02:51 +0530 | [diff] [blame] | 93 | |
Alexander Dahl | e8ffc1d | 2022-07-21 15:31:21 +0200 | [diff] [blame] | 94 | config SYS_FPGA_CHECK_CTRLC |
| 95 | bool "Allow Control-C to interrupt FPGA configuration" |
| 96 | depends on FPGA |
| 97 | help |
| 98 | User can interrupt FPGA configuration by pressing CTRL+C. |
| 99 | |
Alexander Dahl | 8c09cb6 | 2022-07-21 15:31:22 +0200 | [diff] [blame] | 100 | config SYS_FPGA_PROG_FEEDBACK |
| 101 | bool "Progress output during FPGA configuration" |
| 102 | depends on FPGA |
| 103 | default y if FPGA_VIRTEX2 |
| 104 | help |
| 105 | Enable printing of hash marks during FPGA configuration. |
| 106 | |
Oleksandr Suvorov | fb2b885 | 2022-07-22 17:16:02 +0300 | [diff] [blame] | 107 | config FPGA_LOAD_SECURE |
| 108 | bool "Enable loading secure bitstreams" |
| 109 | depends on FPGA |
| 110 | help |
| 111 | Enables the fpga loads() functions that are used to load secure |
| 112 | (authenticated or encrypted or both) bitstreams on to FPGA. |
| 113 | |
| 114 | config SPL_FPGA_LOAD_SECURE |
| 115 | bool "Enable loading secure bitstreams for SPL" |
| 116 | depends on SPL_FPGA |
| 117 | help |
| 118 | Enables the fpga loads() functions that are used to load secure |
| 119 | (authenticated or encrypted or both) bitstreams on to FPGA. |
| 120 | |
Michal Simek | 6ded73a | 2016-09-19 10:41:55 +0200 | [diff] [blame] | 121 | endmenu |