blob: 3b6cf5ddb5049fb5fe126c7558463a57d8bf2127 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Vipin KUMAR5b1b1882010-06-29 10:53:34 +05302/*
3 * (C) Copyright 2010
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
Vipin KUMAR5b1b1882010-06-29 10:53:34 +05305 */
6
7/*
Simon Glass64dcd252015-04-05 16:07:40 -06008 * Designware ethernet IP driver for U-Boot
Vipin KUMAR5b1b1882010-06-29 10:53:34 +05309 */
10
11#include <common.h>
Patrice Chotardba1f9662017-11-29 09:06:11 +010012#include <clk.h>
Simon Glass75577ba2015-04-05 16:07:41 -060013#include <dm.h>
Simon Glass64dcd252015-04-05 16:07:40 -060014#include <errno.h>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053015#include <miiphy.h>
16#include <malloc.h>
Bin Meng8b7ee662015-09-11 03:24:35 -070017#include <pci.h>
Ley Foon Tan495c70f2018-06-14 18:45:23 +080018#include <reset.h>
Stefan Roeseef760252012-05-07 12:04:25 +020019#include <linux/compiler.h>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053020#include <linux/err.h>
Florian Fainelli7a9ca9d2017-12-09 14:59:55 -080021#include <linux/kernel.h>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053022#include <asm/io.h>
Jacob Chen6ec922f2017-03-27 16:54:17 +080023#include <power/regulator.h>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053024#include "designware.h"
25
Alexey Brodkin92a190a2014-01-22 20:54:06 +040026static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
27{
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010028#ifdef CONFIG_DM_ETH
29 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
30 struct eth_mac_regs *mac_p = priv->mac_regs_p;
31#else
Alexey Brodkin92a190a2014-01-22 20:54:06 +040032 struct eth_mac_regs *mac_p = bus->priv;
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010033#endif
Alexey Brodkin92a190a2014-01-22 20:54:06 +040034 ulong start;
35 u16 miiaddr;
36 int timeout = CONFIG_MDIO_TIMEOUT;
37
38 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
39 ((reg << MIIREGSHIFT) & MII_REGMSK);
40
41 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
42
43 start = get_timer(0);
44 while (get_timer(start) < timeout) {
45 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
46 return readl(&mac_p->miidata);
47 udelay(10);
48 };
49
Simon Glass64dcd252015-04-05 16:07:40 -060050 return -ETIMEDOUT;
Alexey Brodkin92a190a2014-01-22 20:54:06 +040051}
52
53static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
54 u16 val)
55{
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010056#ifdef CONFIG_DM_ETH
57 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
58 struct eth_mac_regs *mac_p = priv->mac_regs_p;
59#else
Alexey Brodkin92a190a2014-01-22 20:54:06 +040060 struct eth_mac_regs *mac_p = bus->priv;
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010061#endif
Alexey Brodkin92a190a2014-01-22 20:54:06 +040062 ulong start;
63 u16 miiaddr;
Simon Glass64dcd252015-04-05 16:07:40 -060064 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
Alexey Brodkin92a190a2014-01-22 20:54:06 +040065
66 writel(val, &mac_p->miidata);
67 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
68 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
69
70 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
71
72 start = get_timer(0);
73 while (get_timer(start) < timeout) {
74 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
75 ret = 0;
76 break;
77 }
78 udelay(10);
79 };
80
81 return ret;
82}
83
Alexey Brodkin66d027e2016-06-27 13:17:51 +030084#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010085static int dw_mdio_reset(struct mii_dev *bus)
86{
87 struct udevice *dev = bus->priv;
88 struct dw_eth_dev *priv = dev_get_priv(dev);
89 struct dw_eth_pdata *pdata = dev_get_platdata(dev);
90 int ret;
91
92 if (!dm_gpio_is_valid(&priv->reset_gpio))
93 return 0;
94
95 /* reset the phy */
96 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
97 if (ret)
98 return ret;
99
100 udelay(pdata->reset_delays[0]);
101
102 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
103 if (ret)
104 return ret;
105
106 udelay(pdata->reset_delays[1]);
107
108 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
109 if (ret)
110 return ret;
111
112 udelay(pdata->reset_delays[2]);
113
114 return 0;
115}
116#endif
117
118static int dw_mdio_init(const char *name, void *priv)
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400119{
120 struct mii_dev *bus = mdio_alloc();
121
122 if (!bus) {
123 printf("Failed to allocate MDIO bus\n");
Simon Glass64dcd252015-04-05 16:07:40 -0600124 return -ENOMEM;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400125 }
126
127 bus->read = dw_mdio_read;
128 bus->write = dw_mdio_write;
Ben Whitten192bc692015-12-30 13:05:58 +0000129 snprintf(bus->name, sizeof(bus->name), "%s", name);
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300130#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100131 bus->reset = dw_mdio_reset;
132#endif
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400133
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100134 bus->priv = priv;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400135
136 return mdio_register(bus);
137}
Vipin Kumar13edd172012-03-26 00:09:56 +0000138
Simon Glass64dcd252015-04-05 16:07:40 -0600139static void tx_descs_init(struct dw_eth_dev *priv)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530140{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530141 struct eth_dma_regs *dma_p = priv->dma_regs_p;
142 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
143 char *txbuffs = &priv->txbuffs[0];
144 struct dmamacdescr *desc_p;
145 u32 idx;
146
147 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
148 desc_p = &desc_table_p[idx];
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200149 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
150 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530151
152#if defined(CONFIG_DW_ALTDESCRIPTOR)
153 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
Marek Vasut2b261092015-12-20 03:59:23 +0100154 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
155 DESC_TXSTS_TXCHECKINSCTRL |
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530156 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
157
158 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
159 desc_p->dmamac_cntl = 0;
160 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
161#else
162 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
163 desc_p->txrx_status = 0;
164#endif
165 }
166
167 /* Correcting the last pointer of the chain */
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200168 desc_p->dmamac_next = (ulong)&desc_table_p[0];
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530169
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400170 /* Flush all Tx buffer descriptors at once */
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200171 flush_dcache_range((ulong)priv->tx_mac_descrtable,
172 (ulong)priv->tx_mac_descrtable +
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400173 sizeof(priv->tx_mac_descrtable));
174
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530175 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
Alexey Brodkin74cb7082014-01-13 13:28:38 +0400176 priv->tx_currdescnum = 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530177}
178
Simon Glass64dcd252015-04-05 16:07:40 -0600179static void rx_descs_init(struct dw_eth_dev *priv)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530180{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530181 struct eth_dma_regs *dma_p = priv->dma_regs_p;
182 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
183 char *rxbuffs = &priv->rxbuffs[0];
184 struct dmamacdescr *desc_p;
185 u32 idx;
186
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400187 /* Before passing buffers to GMAC we need to make sure zeros
188 * written there right after "priv" structure allocation were
189 * flushed into RAM.
190 * Otherwise there's a chance to get some of them flushed in RAM when
191 * GMAC is already pushing data to RAM via DMA. This way incoming from
192 * GMAC data will be corrupted. */
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200193 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400194
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530195 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
196 desc_p = &desc_table_p[idx];
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200197 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
198 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530199
200 desc_p->dmamac_cntl =
Marek Vasut2b261092015-12-20 03:59:23 +0100201 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530202 DESC_RXCTRL_RXCHAIN;
203
204 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
205 }
206
207 /* Correcting the last pointer of the chain */
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200208 desc_p->dmamac_next = (ulong)&desc_table_p[0];
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530209
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400210 /* Flush all Rx buffer descriptors at once */
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200211 flush_dcache_range((ulong)priv->rx_mac_descrtable,
212 (ulong)priv->rx_mac_descrtable +
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400213 sizeof(priv->rx_mac_descrtable));
214
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530215 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
Alexey Brodkin74cb7082014-01-13 13:28:38 +0400216 priv->rx_currdescnum = 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530217}
218
Simon Glass64dcd252015-04-05 16:07:40 -0600219static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530220{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530221 struct eth_mac_regs *mac_p = priv->mac_regs_p;
222 u32 macid_lo, macid_hi;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530223
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400224 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
225 (mac_id[3] << 24);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530226 macid_hi = mac_id[4] + (mac_id[5] << 8);
227
228 writel(macid_hi, &mac_p->macaddr0hi);
229 writel(macid_lo, &mac_p->macaddr0lo);
230
231 return 0;
232}
233
Simon Glass0ea38db2017-01-11 11:46:08 +0100234static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
235 struct phy_device *phydev)
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400236{
237 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
238
239 if (!phydev->link) {
240 printf("%s: No link.\n", phydev->dev->name);
Simon Glass0ea38db2017-01-11 11:46:08 +0100241 return 0;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400242 }
243
244 if (phydev->speed != 1000)
245 conf |= MII_PORTSELECT;
Alexey Brodkinb884c3f2016-01-13 16:59:36 +0300246 else
247 conf &= ~MII_PORTSELECT;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400248
249 if (phydev->speed == 100)
250 conf |= FES_100;
251
252 if (phydev->duplex)
253 conf |= FULLDPLXMODE;
254
255 writel(conf, &mac_p->conf);
256
257 printf("Speed: %d, %s duplex%s\n", phydev->speed,
258 (phydev->duplex) ? "full" : "half",
259 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
Simon Glass0ea38db2017-01-11 11:46:08 +0100260
261 return 0;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400262}
263
Simon Glass64dcd252015-04-05 16:07:40 -0600264static void _dw_eth_halt(struct dw_eth_dev *priv)
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400265{
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400266 struct eth_mac_regs *mac_p = priv->mac_regs_p;
267 struct eth_dma_regs *dma_p = priv->dma_regs_p;
268
269 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
270 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
271
272 phy_shutdown(priv->phydev);
273}
274
Simon Glasse72ced22017-01-11 11:46:10 +0100275int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530276{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530277 struct eth_mac_regs *mac_p = priv->mac_regs_p;
278 struct eth_dma_regs *dma_p = priv->dma_regs_p;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400279 unsigned int start;
Simon Glass64dcd252015-04-05 16:07:40 -0600280 int ret;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530281
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400282 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
Vipin Kumar13edd172012-03-26 00:09:56 +0000283
Quentin Schulzc6122192018-06-04 12:17:33 +0200284 /*
285 * When a MII PHY is used, we must set the PS bit for the DMA
286 * reset to succeed.
287 */
288 if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
289 writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
290 else
291 writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
292
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400293 start = get_timer(0);
294 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
Alexey Brodkin875143f2015-01-13 17:10:24 +0300295 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
296 printf("DMA reset timeout\n");
Simon Glass64dcd252015-04-05 16:07:40 -0600297 return -ETIMEDOUT;
Alexey Brodkin875143f2015-01-13 17:10:24 +0300298 }
Stefan Roeseef760252012-05-07 12:04:25 +0200299
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400300 mdelay(100);
301 };
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530302
Bin Mengf3edfd32015-06-15 18:40:19 +0800303 /*
304 * Soft reset above clears HW address registers.
305 * So we have to set it here once again.
306 */
307 _dw_write_hwaddr(priv, enetaddr);
308
Simon Glass64dcd252015-04-05 16:07:40 -0600309 rx_descs_init(priv);
310 tx_descs_init(priv);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530311
Ian Campbell49692c52014-05-08 22:26:35 +0100312 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530313
Sonic Zhangd2279222015-01-29 14:38:50 +0800314#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400315 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
316 &dma_p->opmode);
Sonic Zhangd2279222015-01-29 14:38:50 +0800317#else
318 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
319 &dma_p->opmode);
320#endif
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530321
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400322 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530323
Sonic Zhang2ddaf132015-01-29 13:37:31 +0800324#ifdef CONFIG_DW_AXI_BURST_LEN
325 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
326#endif
327
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400328 /* Start up the PHY */
Simon Glass64dcd252015-04-05 16:07:40 -0600329 ret = phy_startup(priv->phydev);
330 if (ret) {
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400331 printf("Could not initialize PHY %s\n",
332 priv->phydev->dev->name);
Simon Glass64dcd252015-04-05 16:07:40 -0600333 return ret;
Vipin Kumar9afc1af2012-05-07 13:06:44 +0530334 }
335
Simon Glass0ea38db2017-01-11 11:46:08 +0100336 ret = dw_adjust_link(priv, mac_p, priv->phydev);
337 if (ret)
338 return ret;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530339
Simon Glassf63f28e2017-01-11 11:46:09 +0100340 return 0;
341}
342
Simon Glasse72ced22017-01-11 11:46:10 +0100343int designware_eth_enable(struct dw_eth_dev *priv)
Simon Glassf63f28e2017-01-11 11:46:09 +0100344{
345 struct eth_mac_regs *mac_p = priv->mac_regs_p;
346
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400347 if (!priv->phydev->link)
Simon Glass64dcd252015-04-05 16:07:40 -0600348 return -EIO;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530349
Armando Viscontiaa510052012-03-26 00:09:55 +0000350 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530351
352 return 0;
353}
354
Florian Fainelli7a9ca9d2017-12-09 14:59:55 -0800355#define ETH_ZLEN 60
356
Simon Glass64dcd252015-04-05 16:07:40 -0600357static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530358{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530359 struct eth_dma_regs *dma_p = priv->dma_regs_p;
360 u32 desc_num = priv->tx_currdescnum;
361 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200362 ulong desc_start = (ulong)desc_p;
363 ulong desc_end = desc_start +
Marek Vasut96cec172014-09-15 01:05:23 +0200364 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200365 ulong data_start = desc_p->dmamac_addr;
366 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
Ian Campbell964ea7c2014-05-08 22:26:33 +0100367 /*
368 * Strictly we only need to invalidate the "txrx_status" field
369 * for the following check, but on some platforms we cannot
Marek Vasut96cec172014-09-15 01:05:23 +0200370 * invalidate only 4 bytes, so we flush the entire descriptor,
371 * which is 16 bytes in total. This is safe because the
372 * individual descriptors in the array are each aligned to
373 * ARCH_DMA_MINALIGN and padded appropriately.
Ian Campbell964ea7c2014-05-08 22:26:33 +0100374 */
Marek Vasut96cec172014-09-15 01:05:23 +0200375 invalidate_dcache_range(desc_start, desc_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400376
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530377 /* Check if the descriptor is owned by CPU */
378 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
379 printf("CPU not owner of tx frame\n");
Simon Glass64dcd252015-04-05 16:07:40 -0600380 return -EPERM;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530381 }
382
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200383 memcpy((void *)data_start, packet, length);
Simon Goldschmidt7efb75b2018-11-17 10:24:42 +0100384 if (length < ETH_ZLEN) {
385 memset(&((char *)data_start)[length], 0, ETH_ZLEN - length);
386 length = ETH_ZLEN;
387 }
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530388
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400389 /* Flush data to be sent */
Marek Vasut96cec172014-09-15 01:05:23 +0200390 flush_dcache_range(data_start, data_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400391
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530392#if defined(CONFIG_DW_ALTDESCRIPTOR)
393 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
Simon Goldschmidtae8ac8d2018-11-17 10:24:41 +0100394 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
395 ((length << DESC_TXCTRL_SIZE1SHFT) &
396 DESC_TXCTRL_SIZE1MASK);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530397
398 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
399 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
400#else
Simon Goldschmidtae8ac8d2018-11-17 10:24:41 +0100401 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
402 ((length << DESC_TXCTRL_SIZE1SHFT) &
403 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
404 DESC_TXCTRL_TXFIRST;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530405
406 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
407#endif
408
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400409 /* Flush modified buffer descriptor */
Marek Vasut96cec172014-09-15 01:05:23 +0200410 flush_dcache_range(desc_start, desc_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400411
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530412 /* Test the wrap-around condition. */
413 if (++desc_num >= CONFIG_TX_DESCR_NUM)
414 desc_num = 0;
415
416 priv->tx_currdescnum = desc_num;
417
418 /* Start the transmission */
419 writel(POLL_DATA, &dma_p->txpolldemand);
420
421 return 0;
422}
423
Simon Glass75577ba2015-04-05 16:07:41 -0600424static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530425{
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400426 u32 status, desc_num = priv->rx_currdescnum;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530427 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
Simon Glass75577ba2015-04-05 16:07:41 -0600428 int length = -EAGAIN;
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200429 ulong desc_start = (ulong)desc_p;
430 ulong desc_end = desc_start +
Marek Vasut96cec172014-09-15 01:05:23 +0200431 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200432 ulong data_start = desc_p->dmamac_addr;
433 ulong data_end;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530434
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400435 /* Invalidate entire buffer descriptor */
Marek Vasut96cec172014-09-15 01:05:23 +0200436 invalidate_dcache_range(desc_start, desc_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400437
438 status = desc_p->txrx_status;
439
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530440 /* Check if the owner is the CPU */
441 if (!(status & DESC_RXSTS_OWNBYDMA)) {
442
Marek Vasut2b261092015-12-20 03:59:23 +0100443 length = (status & DESC_RXSTS_FRMLENMSK) >>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530444 DESC_RXSTS_FRMLENSHFT;
445
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400446 /* Invalidate received data */
Marek Vasut96cec172014-09-15 01:05:23 +0200447 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
448 invalidate_dcache_range(data_start, data_end);
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200449 *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530450 }
451
Simon Glass75577ba2015-04-05 16:07:41 -0600452 return length;
453}
454
455static int _dw_free_pkt(struct dw_eth_dev *priv)
456{
457 u32 desc_num = priv->rx_currdescnum;
458 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200459 ulong desc_start = (ulong)desc_p;
460 ulong desc_end = desc_start +
Simon Glass75577ba2015-04-05 16:07:41 -0600461 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
462
463 /*
464 * Make the current descriptor valid again and go to
465 * the next one
466 */
467 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
468
469 /* Flush only status field - others weren't changed */
470 flush_dcache_range(desc_start, desc_end);
471
472 /* Test the wrap-around condition. */
473 if (++desc_num >= CONFIG_RX_DESCR_NUM)
474 desc_num = 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530475 priv->rx_currdescnum = desc_num;
476
Simon Glass75577ba2015-04-05 16:07:41 -0600477 return 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530478}
479
Simon Glass64dcd252015-04-05 16:07:40 -0600480static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530481{
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400482 struct phy_device *phydev;
Alexey Brodkin6968ec92016-01-13 16:59:37 +0300483 int mask = 0xffffffff, ret;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530484
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400485#ifdef CONFIG_PHY_ADDR
486 mask = 1 << CONFIG_PHY_ADDR;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530487#endif
488
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400489 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
490 if (!phydev)
Simon Glass64dcd252015-04-05 16:07:40 -0600491 return -ENODEV;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530492
Ian Campbell15e82e52014-04-28 20:14:05 +0100493 phy_connect_dev(phydev, dev);
494
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400495 phydev->supported &= PHY_GBIT_FEATURES;
Alexey Brodkin6968ec92016-01-13 16:59:37 +0300496 if (priv->max_speed) {
497 ret = phy_set_supported(phydev, priv->max_speed);
498 if (ret)
499 return ret;
500 }
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400501 phydev->advertising = phydev->supported;
502
503 priv->phydev = phydev;
504 phy_config(phydev);
505
Simon Glass64dcd252015-04-05 16:07:40 -0600506 return 0;
507}
508
Simon Glass75577ba2015-04-05 16:07:41 -0600509#ifndef CONFIG_DM_ETH
Simon Glass64dcd252015-04-05 16:07:40 -0600510static int dw_eth_init(struct eth_device *dev, bd_t *bis)
511{
Simon Glassf63f28e2017-01-11 11:46:09 +0100512 int ret;
513
Simon Glasse72ced22017-01-11 11:46:10 +0100514 ret = designware_eth_init(dev->priv, dev->enetaddr);
Simon Glassf63f28e2017-01-11 11:46:09 +0100515 if (!ret)
516 ret = designware_eth_enable(dev->priv);
517
518 return ret;
Simon Glass64dcd252015-04-05 16:07:40 -0600519}
520
521static int dw_eth_send(struct eth_device *dev, void *packet, int length)
522{
523 return _dw_eth_send(dev->priv, packet, length);
524}
525
526static int dw_eth_recv(struct eth_device *dev)
527{
Simon Glass75577ba2015-04-05 16:07:41 -0600528 uchar *packet;
529 int length;
530
531 length = _dw_eth_recv(dev->priv, &packet);
532 if (length == -EAGAIN)
533 return 0;
534 net_process_received_packet(packet, length);
535
536 _dw_free_pkt(dev->priv);
537
538 return 0;
Simon Glass64dcd252015-04-05 16:07:40 -0600539}
540
541static void dw_eth_halt(struct eth_device *dev)
542{
543 return _dw_eth_halt(dev->priv);
544}
545
546static int dw_write_hwaddr(struct eth_device *dev)
547{
548 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530549}
550
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400551int designware_initialize(ulong base_addr, u32 interface)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530552{
553 struct eth_device *dev;
554 struct dw_eth_dev *priv;
555
556 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
557 if (!dev)
558 return -ENOMEM;
559
560 /*
561 * Since the priv structure contains the descriptors which need a strict
562 * buswidth alignment, memalign is used to allocate memory
563 */
Ian Campbell1c848a22014-05-08 22:26:32 +0100564 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
565 sizeof(struct dw_eth_dev));
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530566 if (!priv) {
567 free(dev);
568 return -ENOMEM;
569 }
570
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200571 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
572 printf("designware: buffers are outside DMA memory\n");
573 return -EINVAL;
574 }
575
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530576 memset(dev, 0, sizeof(struct eth_device));
577 memset(priv, 0, sizeof(struct dw_eth_dev));
578
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400579 sprintf(dev->name, "dwmac.%lx", base_addr);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530580 dev->iobase = (int)base_addr;
581 dev->priv = priv;
582
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530583 priv->dev = dev;
584 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
585 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
586 DW_DMA_BASE_OFFSET);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530587
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530588 dev->init = dw_eth_init;
589 dev->send = dw_eth_send;
590 dev->recv = dw_eth_recv;
591 dev->halt = dw_eth_halt;
592 dev->write_hwaddr = dw_write_hwaddr;
593
594 eth_register(dev);
595
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400596 priv->interface = interface;
597
598 dw_mdio_init(dev->name, priv->mac_regs_p);
599 priv->bus = miiphy_get_dev_by_name(dev->name);
600
Simon Glass64dcd252015-04-05 16:07:40 -0600601 return dw_phy_init(priv, dev);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530602}
Simon Glass75577ba2015-04-05 16:07:41 -0600603#endif
604
605#ifdef CONFIG_DM_ETH
606static int designware_eth_start(struct udevice *dev)
607{
608 struct eth_pdata *pdata = dev_get_platdata(dev);
Simon Glassf63f28e2017-01-11 11:46:09 +0100609 struct dw_eth_dev *priv = dev_get_priv(dev);
610 int ret;
Simon Glass75577ba2015-04-05 16:07:41 -0600611
Simon Glasse72ced22017-01-11 11:46:10 +0100612 ret = designware_eth_init(priv, pdata->enetaddr);
Simon Glassf63f28e2017-01-11 11:46:09 +0100613 if (ret)
614 return ret;
615 ret = designware_eth_enable(priv);
616 if (ret)
617 return ret;
618
619 return 0;
Simon Glass75577ba2015-04-05 16:07:41 -0600620}
621
Simon Glasse72ced22017-01-11 11:46:10 +0100622int designware_eth_send(struct udevice *dev, void *packet, int length)
Simon Glass75577ba2015-04-05 16:07:41 -0600623{
624 struct dw_eth_dev *priv = dev_get_priv(dev);
625
626 return _dw_eth_send(priv, packet, length);
627}
628
Simon Glasse72ced22017-01-11 11:46:10 +0100629int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
Simon Glass75577ba2015-04-05 16:07:41 -0600630{
631 struct dw_eth_dev *priv = dev_get_priv(dev);
632
633 return _dw_eth_recv(priv, packetp);
634}
635
Simon Glasse72ced22017-01-11 11:46:10 +0100636int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
Simon Glass75577ba2015-04-05 16:07:41 -0600637{
638 struct dw_eth_dev *priv = dev_get_priv(dev);
639
640 return _dw_free_pkt(priv);
641}
642
Simon Glasse72ced22017-01-11 11:46:10 +0100643void designware_eth_stop(struct udevice *dev)
Simon Glass75577ba2015-04-05 16:07:41 -0600644{
645 struct dw_eth_dev *priv = dev_get_priv(dev);
646
647 return _dw_eth_halt(priv);
648}
649
Simon Glasse72ced22017-01-11 11:46:10 +0100650int designware_eth_write_hwaddr(struct udevice *dev)
Simon Glass75577ba2015-04-05 16:07:41 -0600651{
652 struct eth_pdata *pdata = dev_get_platdata(dev);
653 struct dw_eth_dev *priv = dev_get_priv(dev);
654
655 return _dw_write_hwaddr(priv, pdata->enetaddr);
656}
657
Bin Meng8b7ee662015-09-11 03:24:35 -0700658static int designware_eth_bind(struct udevice *dev)
659{
660#ifdef CONFIG_DM_PCI
661 static int num_cards;
662 char name[20];
663
664 /* Create a unique device name for PCI type devices */
665 if (device_is_on_pci_bus(dev)) {
666 sprintf(name, "eth_designware#%u", num_cards++);
667 device_set_name(dev, name);
668 }
669#endif
670
671 return 0;
672}
673
Sjoerd Simonsb9e08d02017-01-11 11:46:07 +0100674int designware_eth_probe(struct udevice *dev)
Simon Glass75577ba2015-04-05 16:07:41 -0600675{
676 struct eth_pdata *pdata = dev_get_platdata(dev);
677 struct dw_eth_dev *priv = dev_get_priv(dev);
Bin Mengf0dc73c2015-09-03 05:37:29 -0700678 u32 iobase = pdata->iobase;
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200679 ulong ioaddr;
Simon Goldschmidt4ee587e2019-07-12 21:07:03 +0200680 int ret, err;
Ley Foon Tan495c70f2018-06-14 18:45:23 +0800681 struct reset_ctl_bulk reset_bulk;
Patrice Chotardba1f9662017-11-29 09:06:11 +0100682#ifdef CONFIG_CLK
Simon Goldschmidt4ee587e2019-07-12 21:07:03 +0200683 int i, clock_nb;
Patrice Chotardba1f9662017-11-29 09:06:11 +0100684
685 priv->clock_count = 0;
686 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
687 if (clock_nb > 0) {
688 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
689 GFP_KERNEL);
690 if (!priv->clocks)
691 return -ENOMEM;
692
693 for (i = 0; i < clock_nb; i++) {
694 err = clk_get_by_index(dev, i, &priv->clocks[i]);
695 if (err < 0)
696 break;
697
698 err = clk_enable(&priv->clocks[i]);
Eugeniy Paltsev1693a572018-02-06 17:12:09 +0300699 if (err && err != -ENOSYS && err != -ENOTSUPP) {
Patrice Chotardba1f9662017-11-29 09:06:11 +0100700 pr_err("failed to enable clock %d\n", i);
701 clk_free(&priv->clocks[i]);
702 goto clk_err;
703 }
704 priv->clock_count++;
705 }
706 } else if (clock_nb != -ENOENT) {
707 pr_err("failed to get clock phandle(%d)\n", clock_nb);
708 return clock_nb;
709 }
710#endif
Simon Glass75577ba2015-04-05 16:07:41 -0600711
Jacob Chen6ec922f2017-03-27 16:54:17 +0800712#if defined(CONFIG_DM_REGULATOR)
713 struct udevice *phy_supply;
714
715 ret = device_get_supply_regulator(dev, "phy-supply",
716 &phy_supply);
717 if (ret) {
718 debug("%s: No phy supply\n", dev->name);
719 } else {
720 ret = regulator_set_enable(phy_supply, true);
721 if (ret) {
722 puts("Error enabling phy supply\n");
723 return ret;
724 }
725 }
726#endif
727
Ley Foon Tan495c70f2018-06-14 18:45:23 +0800728 ret = reset_get_bulk(dev, &reset_bulk);
729 if (ret)
730 dev_warn(dev, "Can't get reset: %d\n", ret);
731 else
732 reset_deassert_bulk(&reset_bulk);
733
Bin Meng8b7ee662015-09-11 03:24:35 -0700734#ifdef CONFIG_DM_PCI
735 /*
736 * If we are on PCI bus, either directly attached to a PCI root port,
737 * or via a PCI bridge, fill in platdata before we probe the hardware.
738 */
739 if (device_is_on_pci_bus(dev)) {
Bin Meng8b7ee662015-09-11 03:24:35 -0700740 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
741 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
Bin Meng6758a6c2016-02-02 05:58:00 -0800742 iobase = dm_pci_mem_to_phys(dev, iobase);
Bin Meng8b7ee662015-09-11 03:24:35 -0700743
744 pdata->iobase = iobase;
745 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
746 }
747#endif
748
Bin Mengf0dc73c2015-09-03 05:37:29 -0700749 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200750 ioaddr = iobase;
751 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
752 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
Simon Glass75577ba2015-04-05 16:07:41 -0600753 priv->interface = pdata->phy_interface;
Alexey Brodkin6968ec92016-01-13 16:59:37 +0300754 priv->max_speed = pdata->max_speed;
Simon Glass75577ba2015-04-05 16:07:41 -0600755
Simon Goldschmidt4ee587e2019-07-12 21:07:03 +0200756 ret = dw_mdio_init(dev->name, dev);
757 if (ret) {
758 err = ret;
759 goto mdio_err;
760 }
Simon Glass75577ba2015-04-05 16:07:41 -0600761 priv->bus = miiphy_get_dev_by_name(dev->name);
762
763 ret = dw_phy_init(priv, dev);
764 debug("%s, ret=%d\n", __func__, ret);
Simon Goldschmidt4ee587e2019-07-12 21:07:03 +0200765 if (!ret)
766 return 0;
Simon Glass75577ba2015-04-05 16:07:41 -0600767
Simon Goldschmidt4ee587e2019-07-12 21:07:03 +0200768 /* continue here for cleanup if no PHY found */
769 err = ret;
770 mdio_unregister(priv->bus);
771 mdio_free(priv->bus);
772mdio_err:
Patrice Chotardba1f9662017-11-29 09:06:11 +0100773
774#ifdef CONFIG_CLK
775clk_err:
776 ret = clk_release_all(priv->clocks, priv->clock_count);
777 if (ret)
778 pr_err("failed to disable all clocks\n");
779
Patrice Chotardba1f9662017-11-29 09:06:11 +0100780#endif
Simon Goldschmidt4ee587e2019-07-12 21:07:03 +0200781 return err;
Simon Glass75577ba2015-04-05 16:07:41 -0600782}
783
Bin Meng5d2459f2015-10-07 21:32:38 -0700784static int designware_eth_remove(struct udevice *dev)
785{
786 struct dw_eth_dev *priv = dev_get_priv(dev);
787
788 free(priv->phydev);
789 mdio_unregister(priv->bus);
790 mdio_free(priv->bus);
791
Patrice Chotardba1f9662017-11-29 09:06:11 +0100792#ifdef CONFIG_CLK
793 return clk_release_all(priv->clocks, priv->clock_count);
794#else
Bin Meng5d2459f2015-10-07 21:32:38 -0700795 return 0;
Patrice Chotardba1f9662017-11-29 09:06:11 +0100796#endif
Bin Meng5d2459f2015-10-07 21:32:38 -0700797}
798
Sjoerd Simonsb9e08d02017-01-11 11:46:07 +0100799const struct eth_ops designware_eth_ops = {
Simon Glass75577ba2015-04-05 16:07:41 -0600800 .start = designware_eth_start,
801 .send = designware_eth_send,
802 .recv = designware_eth_recv,
803 .free_pkt = designware_eth_free_pkt,
804 .stop = designware_eth_stop,
805 .write_hwaddr = designware_eth_write_hwaddr,
806};
807
Sjoerd Simonsb9e08d02017-01-11 11:46:07 +0100808int designware_eth_ofdata_to_platdata(struct udevice *dev)
Simon Glass75577ba2015-04-05 16:07:41 -0600809{
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100810 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300811#ifdef CONFIG_DM_GPIO
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100812 struct dw_eth_dev *priv = dev_get_priv(dev);
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300813#endif
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100814 struct eth_pdata *pdata = &dw_pdata->eth_pdata;
Simon Glass75577ba2015-04-05 16:07:41 -0600815 const char *phy_mode;
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300816#ifdef CONFIG_DM_GPIO
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100817 int reset_flags = GPIOD_IS_OUT;
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300818#endif
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100819 int ret = 0;
Simon Glass75577ba2015-04-05 16:07:41 -0600820
Philipp Tomsich15050f12017-09-11 22:04:13 +0200821 pdata->iobase = dev_read_addr(dev);
Simon Glass75577ba2015-04-05 16:07:41 -0600822 pdata->phy_interface = -1;
Philipp Tomsich15050f12017-09-11 22:04:13 +0200823 phy_mode = dev_read_string(dev, "phy-mode");
Simon Glass75577ba2015-04-05 16:07:41 -0600824 if (phy_mode)
825 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
826 if (pdata->phy_interface == -1) {
827 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
828 return -EINVAL;
829 }
830
Philipp Tomsich15050f12017-09-11 22:04:13 +0200831 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
Alexey Brodkin6968ec92016-01-13 16:59:37 +0300832
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300833#ifdef CONFIG_DM_GPIO
Philipp Tomsich7ad326a2017-06-07 18:46:01 +0200834 if (dev_read_bool(dev, "snps,reset-active-low"))
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100835 reset_flags |= GPIOD_ACTIVE_LOW;
836
837 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
838 &priv->reset_gpio, reset_flags);
839 if (ret == 0) {
Philipp Tomsich7ad326a2017-06-07 18:46:01 +0200840 ret = dev_read_u32_array(dev, "snps,reset-delays-us",
841 dw_pdata->reset_delays, 3);
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100842 } else if (ret == -ENOENT) {
843 ret = 0;
844 }
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300845#endif
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100846
847 return ret;
Simon Glass75577ba2015-04-05 16:07:41 -0600848}
849
850static const struct udevice_id designware_eth_ids[] = {
851 { .compatible = "allwinner,sun7i-a20-gmac" },
Marek Vasutb9628592015-07-25 18:38:44 +0200852 { .compatible = "altr,socfpga-stmmac" },
Beniamino Galvanicfe25562016-08-16 11:49:50 +0200853 { .compatible = "amlogic,meson6-dwmac" },
Heiner Kallweit655217d2017-01-27 21:25:59 +0100854 { .compatible = "amlogic,meson-gx-dwmac" },
Neil Armstrongec353ad2018-09-10 16:44:14 +0200855 { .compatible = "amlogic,meson-gxbb-dwmac" },
Neil Armstrong71a38a82018-11-08 17:16:11 +0100856 { .compatible = "amlogic,meson-axg-dwmac" },
Michael Kurzb20b70f2017-01-22 16:04:27 +0100857 { .compatible = "st,stm32-dwmac" },
Simon Glass75577ba2015-04-05 16:07:41 -0600858 { }
859};
860
Marek Vasut9f76f102015-07-25 18:42:34 +0200861U_BOOT_DRIVER(eth_designware) = {
Simon Glass75577ba2015-04-05 16:07:41 -0600862 .name = "eth_designware",
863 .id = UCLASS_ETH,
864 .of_match = designware_eth_ids,
865 .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
Bin Meng8b7ee662015-09-11 03:24:35 -0700866 .bind = designware_eth_bind,
Simon Glass75577ba2015-04-05 16:07:41 -0600867 .probe = designware_eth_probe,
Bin Meng5d2459f2015-10-07 21:32:38 -0700868 .remove = designware_eth_remove,
Simon Glass75577ba2015-04-05 16:07:41 -0600869 .ops = &designware_eth_ops,
870 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100871 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
Simon Glass75577ba2015-04-05 16:07:41 -0600872 .flags = DM_FLAG_ALLOC_PRIV_DMA,
873};
Bin Meng8b7ee662015-09-11 03:24:35 -0700874
875static struct pci_device_id supported[] = {
876 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
877 { }
878};
879
880U_BOOT_PCI_DEVICE(eth_designware, supported);
Simon Glass75577ba2015-04-05 16:07:41 -0600881#endif