blob: bea80c5d00511b726b05a1aa9362e681760e6f7d [file] [log] [blame]
Lokesh Vutla853f7f52018-08-27 15:59:09 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
Andreas Dannenberg7202af92019-04-29 12:56:44 -05006#include <dt-bindings/pinctrl/k3.h>
Grygorii Strashko736b6c32019-02-05 17:31:26 +05307#include <dt-bindings/dma/k3-udma.h>
Grygorii Strashko6f2929d2019-07-09 10:30:36 +05308#include <dt-bindings/net/ti-dp83867.h>
Lokesh Vutla853f7f52018-08-27 15:59:09 +05309
10/ {
11 chosen {
12 stdout-path = "serial2:115200n8";
13 };
14
15 aliases {
16 serial2 = &main_uart0;
Grygorii Strashko5195c102019-07-09 10:30:35 +053017 ethernet0 = &cpsw_port1;
Lokesh Vutla853f7f52018-08-27 15:59:09 +053018 };
19};
20
21&cbass_main{
22 u-boot,dm-spl;
Lokesh Vutla853f7f52018-08-27 15:59:09 +053023
Lokesh Vutla853f7f52018-08-27 15:59:09 +053024 sdhci1: sdhci@04FA0000 {
Faiz Abbas3a1a0df2019-06-11 00:43:31 +053025 compatible = "ti,am654-sdhci-5.1";
Lokesh Vutla2d0eba32018-11-02 19:51:08 +053026 reg = <0x0 0x4FA0000 0x0 0x1000>,
27 <0x0 0x4FB0000 0x0 0x400>;
Lokesh Vutla853f7f52018-08-27 15:59:09 +053028 clocks = <&k3_clks 48 1>;
Lokesh Vutla355be912019-06-07 19:24:47 +053029 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
Lokesh Vutla853f7f52018-08-27 15:59:09 +053030 max-frequency = <25000000>;
Faiz Abbasbbcfaad2019-06-11 00:43:36 +053031 ti,otap-del-sel = <0x2>;
32 ti,trm-icp = <0x8>;
Lokesh Vutla853f7f52018-08-27 15:59:09 +053033 };
34
35};
36
Lokesh Vutla2d0eba32018-11-02 19:51:08 +053037&cbass_mcu {
38 u-boot,dm-spl;
Grygorii Strashko736b6c32019-02-05 17:31:26 +053039
40 navss_mcu: navss-mcu {
41 compatible = "simple-bus";
42 #address-cells = <2>;
43 #size-cells = <2>;
44 ranges;
45
46 ti,sci-dev-id = <119>;
47
48 mcu_ringacc: ringacc@2b800000 {
49 compatible = "ti,am654-navss-ringacc";
50 reg = <0x0 0x2b800000 0x0 0x400000>,
51 <0x0 0x2b000000 0x0 0x400000>,
52 <0x0 0x28590000 0x0 0x100>,
53 <0x0 0x2a500000 0x0 0x40000>;
54 reg-names = "rt", "fifos",
55 "proxy_gcfg", "proxy_target";
56 ti,num-rings = <286>;
57 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
58 ti,dma-ring-reset-quirk;
59 ti,sci = <&dmsc>;
60 ti,sci-dev-id = <195>;
61 };
62
63 mcu_udmap: udmap@285c0000 {
64 compatible = "ti,k3-navss-udmap";
65 reg = <0x0 0x285c0000 0x0 0x100>,
66 <0x0 0x2a800000 0x0 0x40000>,
67 <0x0 0x2aa00000 0x0 0x40000>;
68 reg-names = "gcfg", "rchanrt", "tchanrt";
69 #dma-cells = <3>;
70
71 ti,ringacc = <&mcu_ringacc>;
72 ti,psil-base = <0x6000>;
73
74 ti,sci = <&dmsc>;
75 ti,sci-dev-id = <194>;
76
77 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
78 <0x2>; /* TX_CHAN */
79 ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
80 <0x4>; /* RX_CHAN */
81 ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
82 dma-coherent;
83 };
84 };
Grygorii Strashko5195c102019-07-09 10:30:35 +053085
86 mcu_conf: scm_conf@40f00000 {
87 compatible = "syscon";
88 reg = <0x0 0x40f00000 0x0 0x20000>;
89 };
90
91 mcu_cpsw: cpsw_nuss@046000000 {
92 compatible = "ti,am654-cpsw-nuss";
93 #address-cells = <2>;
94 #size-cells = <2>;
95 reg = <0x0 0x46000000 0x0 0x200000>;
96 reg-names = "cpsw_nuss";
97 ranges;
98 dma-coherent;
99 clocks = <&k3_clks 5 10>;
100 clock-names = "fck";
Suman Annadcddf0f2019-07-29 11:13:41 -0500101 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
Grygorii Strashko5195c102019-07-09 10:30:35 +0530102 ti,psil-base = <0x7000>;
103
104 dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
105 <&mcu_udmap &mcu_cpsw 1 UDMA_DIR_TX>,
106 <&mcu_udmap &mcu_cpsw 2 UDMA_DIR_TX>,
107 <&mcu_udmap &mcu_cpsw 3 UDMA_DIR_TX>,
108 <&mcu_udmap &mcu_cpsw 4 UDMA_DIR_TX>,
109 <&mcu_udmap &mcu_cpsw 5 UDMA_DIR_TX>,
110 <&mcu_udmap &mcu_cpsw 6 UDMA_DIR_TX>,
111 <&mcu_udmap &mcu_cpsw 7 UDMA_DIR_TX>,
112 <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_RX>;
113 dma-names = "tx0", "tx1", "tx2", "tx3",
114 "tx4", "tx5", "tx6", "tx7",
115 "rx";
116
117 ports {
118 #address-cells = <1>;
119 #size-cells = <0>;
120 host: host@0 {
121 reg = <0>;
122 ti,label = "host";
123 };
124
125 cpsw_port1: port@1 {
126 reg = <1>;
127 ti,mac-only;
128 ti,label = "port1";
129 ti,syscon-efuse = <&mcu_conf 0x200>;
130 };
131 };
132
133 davinci_mdio: mdio {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 bus_freq = <1000000>;
137 };
138
139 ti,psil-config0 {
140 linux,udma-mode = <UDMA_PKT_MODE>;
141 statictr-type = <PSIL_STATIC_TR_NONE>;
142 ti,needs-epib;
143 ti,psd-size = <16>;
144 };
145
146 ti,psil-config1 {
147 linux,udma-mode = <UDMA_PKT_MODE>;
148 statictr-type = <PSIL_STATIC_TR_NONE>;
149 ti,needs-epib;
150 ti,psd-size = <16>;
151 };
152
153 ti,psil-config2 {
154 linux,udma-mode = <UDMA_PKT_MODE>;
155 statictr-type = <PSIL_STATIC_TR_NONE>;
156 ti,needs-epib;
157 ti,psd-size = <16>;
158 };
159
160 ti,psil-config3 {
161 linux,udma-mode = <UDMA_PKT_MODE>;
162 statictr-type = <PSIL_STATIC_TR_NONE>;
163 ti,needs-epib;
164 ti,psd-size = <16>;
165 };
166
167 ti,psil-config4 {
168 linux,udma-mode = <UDMA_PKT_MODE>;
169 statictr-type = <PSIL_STATIC_TR_NONE>;
170 ti,needs-epib;
171 ti,psd-size = <16>;
172 };
173
174 ti,psil-config5 {
175 linux,udma-mode = <UDMA_PKT_MODE>;
176 statictr-type = <PSIL_STATIC_TR_NONE>;
177 ti,needs-epib;
178 ti,psd-size = <16>;
179 };
180
181 ti,psil-config6 {
182 linux,udma-mode = <UDMA_PKT_MODE>;
183 statictr-type = <PSIL_STATIC_TR_NONE>;
184 ti,needs-epib;
185 ti,psd-size = <16>;
186 };
187
188 ti,psil-config7 {
189 linux,udma-mode = <UDMA_PKT_MODE>;
190 statictr-type = <PSIL_STATIC_TR_NONE>;
191 ti,needs-epib;
192 ti,psd-size = <16>;
193 };
194 };
Lokesh Vutla2d0eba32018-11-02 19:51:08 +0530195};
196
197&cbass_wakeup {
198 u-boot,dm-spl;
199};
200
201&secure_proxy_main {
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530202 u-boot,dm-spl;
203};
204
205&dmsc {
206 u-boot,dm-spl;
Lokesh Vutla2d0eba32018-11-02 19:51:08 +0530207 k3_sysreset: sysreset-controller {
208 compatible = "ti,sci-sysreset";
209 u-boot,dm-spl;
210 };
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530211};
212
213&k3_pds {
214 u-boot,dm-spl;
215};
216
217&k3_clks {
218 u-boot,dm-spl;
219};
220
221&k3_reset {
222 u-boot,dm-spl;
223};
224
Andreas Dannenberg7e0363b2019-06-04 18:08:15 -0500225&wkup_pmx0 {
226 u-boot,dm-spl;
227
228 wkup_i2c0_pins_default {
229 u-boot,dm-spl;
230 };
231};
232
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530233&main_pmx0 {
234 u-boot,dm-spl;
235 main_uart0_pins_default: main_uart0_pins_default {
236 pinctrl-single,pins = <
Andreas Dannenberg7202af92019-04-29 12:56:44 -0500237 AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
238 AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
239 AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
240 AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530241 >;
Lokesh Vutla2d0eba32018-11-02 19:51:08 +0530242 u-boot,dm-spl;
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530243 };
244
245 main_mmc0_pins_default: main_mmc0_pins_default {
246 pinctrl-single,pins = <
Andreas Dannenberg7202af92019-04-29 12:56:44 -0500247 AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
248 AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
249 AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
250 AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
251 AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
252 AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
253 AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
254 AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
255 AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
256 AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530257 AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
258 AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530259 >;
Lokesh Vutla2d0eba32018-11-02 19:51:08 +0530260 u-boot,dm-spl;
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530261 };
262
263 main_mmc1_pins_default: main_mmc1_pins_default {
264 pinctrl-single,pins = <
Andreas Dannenberg7202af92019-04-29 12:56:44 -0500265 AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
266 AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
267 AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
268 AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
269 AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
270 AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
271 AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
272 AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530273 >;
Lokesh Vutla2d0eba32018-11-02 19:51:08 +0530274 u-boot,dm-spl;
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530275 };
276
277};
278
279&main_pmx1 {
280 u-boot,dm-spl;
281};
282
Grygorii Strashko6f2929d2019-07-09 10:30:36 +0530283&wkup_pmx0 {
284 mcu_cpsw_pins_default: mcu_cpsw_pins_default {
285 pinctrl-single,pins = <
286 AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
287 AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
288 AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
289 AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
290 AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
291 AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
292 AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
293 AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
294 AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
295 AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
296 AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
297 AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
298 >;
299 };
300
301 mcu_mdio_pins_default: mcu_mdio1_pins_default {
302 pinctrl-single,pins = <
303 AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
304 AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
305 >;
306 };
307};
308
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530309&main_uart0 {
310 u-boot,dm-spl;
311 pinctrl-names = "default";
312 pinctrl-0 = <&main_uart0_pins_default>;
313 status = "okay";
314};
315
316&sdhci0 {
317 u-boot,dm-spl;
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530318};
319
320&sdhci1 {
321 u-boot,dm-spl;
322 status = "okay";
323 pinctrl-names = "default";
324 pinctrl-0 = <&main_mmc1_pins_default>;
325 sdhci-caps-mask = <0x7 0x0>;
Faiz Abbasbbcfaad2019-06-11 00:43:36 +0530326 ti,driver-strength-ohm = <50>;
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530327};
Grygorii Strashko6f2929d2019-07-09 10:30:36 +0530328
329&mcu_cpsw {
330 pinctrl-names = "default";
331 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
332};
333
334&davinci_mdio {
335 phy0: ethernet-phy@0 {
336 reg = <0>;
337 /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
338 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
Grygorii Strashko6f2929d2019-07-09 10:30:36 +0530339 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
340 };
341};
342
343&cpsw_port1 {
Grygorii Strashko5efb6922019-11-18 23:04:47 +0200344 phy-mode = "rgmii-rxid";
Grygorii Strashko6f2929d2019-07-09 10:30:36 +0530345 phy-handle = <&phy0>;
346};
347
348&mcu_cpsw {
349 reg = <0x0 0x46000000 0x0 0x200000>,
350 <0x0 0x40f00200 0x0 0x2>;
351 reg-names = "cpsw_nuss", "mac_efuse";
352
353 cpsw-phy-sel@40f04040 {
354 compatible = "ti,am654-cpsw-phy-sel";
355 reg= <0x0 0x40f04040 0x0 0x4>;
356 reg-names = "gmii-sel";
357 };
358};
Andreas Dannenberg7e0363b2019-06-04 18:08:15 -0500359
360&wkup_i2c0 {
361 u-boot,dm-spl;
362};