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Simon Glass714a5622014-02-26 15:59:14 -07001/dts-v1/;
2
Simon Glasse676f432019-05-18 11:59:48 -06003#include <config.h>
4
Simon Glass714a5622014-02-26 15:59:14 -07005/ {
Simon Glass0b304a22014-10-13 23:41:48 -06006 #address-cells = <1>;
Simon Glass20806e72015-03-05 12:25:13 -07007 #size-cells = <1>;
Simon Glassd63b5b42017-06-15 21:37:53 -06008 model = "sandbox";
Heinrich Schuchardt15ab77c2019-11-09 09:39:01 +01009 compatible = "sandbox";
Simon Glass0b304a22014-10-13 23:41:48 -060010
Simon Glass9569c402015-03-05 12:25:26 -070011 aliases {
Simon Glass46af3602015-04-20 12:37:28 -060012 i2c0 = &i2c_0;
Tom Rini42c64d12020-02-11 12:41:23 -050013 pci0 = &pcic;
Simon Glass46af3602015-04-20 12:37:28 -060014 rtc0 = &rtc_0;
Mario Six957983e2018-08-09 14:51:19 +020015 axi0 = &axi;
Simon Glass87dac6b2019-05-18 11:59:42 -060016 spi0 = &spi;
Simon Glass9569c402015-03-05 12:25:26 -070017 };
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Simon Glasse676f432019-05-18 11:59:48 -060019 memory {
20 reg = <0 CONFIG_SYS_SDRAM_SIZE>;
21 };
22
Heinrich Schuchardt1ecea742020-03-14 12:13:39 +010023 reserved-memory {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 reservation_test0 {
29 size = <0x4000>;
30 alignment = <0x2000>;
31 };
32
33 reservation_test1: restest@a000 {
34 reg = <0x00d0a000 0x2000>;
35 };
36
37 reservation_test2: restest@7000 {
38 reg = <0x00d07000 0x1000>;
39 };
40 };
41
Simon Glasse6c5c942018-10-01 12:22:08 -060042 cros_ec: cros-ec {
Simon Glass3fbb7872015-03-26 09:29:39 -060043 reg = <0 0>;
Simon Glass370746a2020-12-19 10:39:56 -070044 u-boot,dm-pre-proper;
Simon Glass3fbb7872015-03-26 09:29:39 -060045 compatible = "google,cros-ec-sandbox";
Simon Glass39741c02014-02-27 13:25:59 -070046 };
47
Yannick Fertré23f965a2019-10-07 15:29:05 +020048 dsi_host: dsi_host {
49 compatible = "sandbox,dsi-host";
50 status = "okay";
51 };
52
Joe Hershbergerf40a31e2018-07-02 14:47:54 -050053 ethrawbus {
54 compatible = "sandbox,eth-raw-bus";
55 skip-localhost = <0>;
56 };
57
Simon Glassf4d84572015-05-22 15:42:16 -060058 eth@10002000 {
59 compatible = "sandbox,eth";
60 reg = <0x10002000 0x1000>;
61 fake-host-hwaddr = [00 00 66 44 22 00];
62 };
63
Simon Glass46af3602015-04-20 12:37:28 -060064 i2c_0: i2c@0 {
Simon Glass776f96f2014-12-10 08:55:53 -070065 #address-cells = <1>;
66 #size-cells = <0>;
Simon Glass20806e72015-03-05 12:25:13 -070067 reg = <0 0>;
Simon Glass776f96f2014-12-10 08:55:53 -070068 compatible = "sandbox,i2c";
69 clock-frequency = <400000>;
Masahiro Yamada9c6a3c62015-08-27 12:44:30 +090070 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_i2c0>;
Simon Glassfbe27a52020-10-03 11:31:36 -060072 u-boot,dm-pre-reloc;
Simon Glassa89c3a02017-04-10 11:34:51 -060073 };
74
Tom Rini42c64d12020-02-11 12:41:23 -050075 pcic: pci@0 {
Simon Glass9569c402015-03-05 12:25:26 -070076 compatible = "sandbox,pci";
77 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -050078 bus-range = <0x00 0xff>;
Simon Glass9569c402015-03-05 12:25:26 -070079 #address-cells = <3>;
80 #size-cells = <2>;
81 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
82 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Simon Glass282e29e2018-12-10 10:37:45 -070083 };
84
Simon Glass87dac6b2019-05-18 11:59:42 -060085 spi: spi@0 {
Simon Glass370746a2020-12-19 10:39:56 -070086 u-boot,dm-pre-proper;
Simon Glassf4d84572015-05-22 15:42:16 -060087 #address-cells = <1>;
88 #size-cells = <0>;
89 reg = <0 0>;
90 compatible = "sandbox,spi";
91 cs-gpios = <0>, <&gpio_a 0>;
Joe Hershberger3ea143a2015-03-22 17:09:13 -050092 };
Simon Glass714a5622014-02-26 15:59:14 -070093};
Simon Glass3fbb7872015-03-26 09:29:39 -060094
Simon Glassdc8c91a2019-05-18 11:59:41 -060095#include "sandbox.dtsi"
Simon Glass3fbb7872015-03-26 09:29:39 -060096#include "cros-ec-keyboard.dtsi"
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +020097#include "sandbox_pmic.dtsi"