| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | #include <ppc4xx.h> |
| 26 | #include <asm/processor.h> |
| 27 | #include <pci.h> |
| 28 | |
| 29 | |
| 30 | #ifdef CONFIG_SDRAM_BANK0 |
| 31 | |
| 32 | |
| 33 | #define MAGIC0 0x00000000 |
| 34 | #define MAGIC1 0x11111111 |
| 35 | #define MAGIC2 0x22222222 |
| 36 | #define MAGIC3 0x33333333 |
| 37 | #define MAGIC4 0x44444444 |
| 38 | |
| 39 | #define ADDR_ZERO 0x00000000 |
| 40 | #define ADDR_400 0x00000400 |
| 41 | #define ADDR_08MB 0x00800000 |
| 42 | #define ADDR_16MB 0x01000000 |
| 43 | #define ADDR_32MB 0x02000000 |
| 44 | #define ADDR_64MB 0x04000000 |
| 45 | |
| 46 | #define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) |
| 47 | |
| 48 | |
| 49 | /*----------------------------------------------------------------------- |
| 50 | */ |
| 51 | void sdram_init(void) |
| 52 | { |
| 53 | ulong speed; |
| 54 | ulong sdtr1; |
| 55 | ulong rtr; |
| 56 | |
| 57 | /* |
| 58 | * Determine SDRAM speed |
| 59 | */ |
| 60 | speed = get_bus_freq(0); /* parameter not used on ppc4xx */ |
| 61 | |
| 62 | /* |
| 63 | * Support for 100MHz and 133MHz SDRAM |
| 64 | */ |
| 65 | if (speed > 100000000) { |
| 66 | /* |
| 67 | * 133 MHz SDRAM |
| 68 | */ |
| 69 | sdtr1 = 0x01074015; |
| 70 | rtr = 0x07f00000; |
| 71 | } else { |
| 72 | /* |
| 73 | * default: 100 MHz SDRAM |
| 74 | */ |
| 75 | sdtr1 = 0x0086400d; |
| 76 | rtr = 0x05f00000; |
| 77 | } |
| 78 | |
| 79 | /* |
| 80 | * Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4) |
| 81 | */ |
| 82 | mtsdram0(mem_mb0cf, 0x00084001); |
| 83 | |
| 84 | mtsdram0(mem_sdtr1, sdtr1); |
| 85 | mtsdram0(mem_rtr, rtr); |
| 86 | |
| 87 | /* |
| 88 | * Wait for 200us |
| 89 | */ |
| 90 | udelay(200); |
| 91 | |
| 92 | /* |
| 93 | * Set memory controller options reg, MCOPT1. |
| 94 | * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst |
| 95 | * read/prefetch. |
| 96 | */ |
| 97 | mtsdram0(mem_mcopt1, 0x80800000); |
| 98 | |
| 99 | /* |
| 100 | * Wait for 10ms |
| 101 | */ |
| 102 | udelay(10000); |
| 103 | |
| 104 | /* |
| 105 | * Test if 64 MByte are equipped (mirror test) |
| 106 | */ |
| 107 | *(volatile ulong *)ADDR_ZERO = MAGIC0; |
| 108 | *(volatile ulong *)ADDR_08MB = MAGIC1; |
| 109 | *(volatile ulong *)ADDR_16MB = MAGIC2; |
| 110 | *(volatile ulong *)ADDR_32MB = MAGIC3; |
| 111 | |
| 112 | if ((*(volatile ulong *)ADDR_ZERO == MAGIC0) && |
| 113 | (*(volatile ulong *)ADDR_08MB == MAGIC1) && |
| 114 | (*(volatile ulong *)ADDR_16MB == MAGIC2)) { |
| 115 | /* |
| 116 | * OK, 64MB detected -> all done |
| 117 | */ |
| 118 | return; |
| 119 | } |
| 120 | |
| 121 | /* |
| 122 | * Now test for 32 MByte... |
| 123 | */ |
| 124 | |
| 125 | /* |
| 126 | * Disable memory controller. |
| 127 | */ |
| 128 | mtsdram0(mem_mcopt1, 0x00000000); |
| 129 | |
| 130 | /* |
| 131 | * Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4) |
| 132 | */ |
| 133 | mtsdram0(mem_mb0cf, 0x00062001); |
| 134 | |
| 135 | /* |
| 136 | * Set memory controller options reg, MCOPT1. |
| 137 | * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst |
| 138 | * read/prefetch. |
| 139 | */ |
| 140 | mtsdram0(mem_mcopt1, 0x80800000); |
| 141 | |
| 142 | /* |
| 143 | * Wait for 10ms |
| 144 | */ |
| 145 | udelay(10000); |
| 146 | |
| 147 | /* |
| 148 | * Test if 32 MByte are equipped (mirror test) |
| 149 | */ |
| 150 | *(volatile ulong *)ADDR_ZERO = MAGIC0; |
| 151 | *(volatile ulong *)ADDR_400 = MAGIC1; |
| 152 | *(volatile ulong *)ADDR_08MB = MAGIC2; |
| 153 | *(volatile ulong *)ADDR_16MB = MAGIC3; |
| 154 | |
| 155 | if ((*(volatile ulong *)ADDR_ZERO == MAGIC0) && |
| 156 | (*(volatile ulong *)ADDR_400 == MAGIC1) && |
| 157 | (*(volatile ulong *)ADDR_08MB == MAGIC2)) { |
| 158 | /* |
| 159 | * OK, 32MB detected -> all done |
| 160 | */ |
| 161 | return; |
| 162 | } |
| 163 | |
| 164 | /* |
| 165 | * Setup for 16 MByte... |
| 166 | */ |
| 167 | |
| 168 | /* |
| 169 | * Disable memory controller. |
| 170 | */ |
| 171 | mtsdram0(mem_mcopt1, 0x00000000); |
| 172 | |
| 173 | /* |
| 174 | * Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4) |
| 175 | */ |
| 176 | mtsdram0(mem_mb0cf, 0x00046001); |
| 177 | |
| 178 | /* |
| 179 | * Set memory controller options reg, MCOPT1. |
| 180 | * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst |
| 181 | * read/prefetch. |
| 182 | */ |
| 183 | mtsdram0(mem_mcopt1, 0x80800000); |
| 184 | |
| 185 | /* |
| 186 | * Wait for 10ms |
| 187 | */ |
| 188 | udelay(10000); |
| 189 | } |
| 190 | |
| 191 | #endif /* CONFIG_SDRAM_BANK0 */ |