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Stefan Roese8e1a3fe2008-03-11 16:51:17 +01001/*
2 * (C) Copyright 2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <ppc_asm.tmpl>
25#include <config.h>
26#include <asm-ppc/mmu.h>
27
28/**************************************************************************
29 * TLB TABLE
30 *
31 * This table is used by the cpu boot code to setup the initial tlb
32 * entries. Rather than make broad assumptions in the cpu source tree,
33 * this table lets each board set things up however they like.
34 *
35 * Pointer to the table is returned in r1
36 *
37 *************************************************************************/
38 .section .bootpg,"ax"
39 .globl tlbtab
40
41tlbtab:
42 tlbtab_start
43
44 /*
45 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
46 * use the speed up boot process. It is patched after relocation to
47 * enable SA_I
48 */
Stefan Roese71665eb2008-03-03 17:27:02 +010049#ifndef CONFIG_NAND_SPL
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050 tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
Stefan Roese71665eb2008-03-03 17:27:02 +010051#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052 tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
53 tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
Stefan Roese499e7832008-04-08 10:33:29 +020054 tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
Stefan Roese71665eb2008-03-03 17:27:02 +010055#endif
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010056
57 /*
58 * TLB entries for SDRAM are not needed on this platform.
59 * They are dynamically generated in the SPD DDR(2) detection
60 * routine.
61 */
62
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#ifdef CONFIG_SYS_INIT_RAM_DCACHE
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010064 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065 tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010066#endif
67
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
69 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
70 tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010071
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
73 tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
74 tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
75 tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010076
77 /* PCIe UTL register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078 tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010079
Adam Grahamf09f09d2008-10-08 10:12:53 -070080#if !defined(CONFIG_ARCHES)
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010081 /* TLB-entry for NAND */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082 tlbentry(CONFIG_SYS_NAND_ADDR, SZ_16M, CONFIG_SYS_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010083
84 /* TLB-entry for CPLD */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085 tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
Adam Grahamf09f09d2008-10-08 10:12:53 -070086#else
87 /* TLB-entry for FPGA */
88 tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_R|AC_W|SA_G|SA_I)
89#endif
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010090
91 /* TLB-entry for OCM */
Dave Mitchellddf45cc2008-11-20 14:09:50 -060092 tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010093
94 /* TLB-entry for Local Configuration registers => peripherals */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095 tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010096
Stefan Roese41712b42008-03-05 12:31:53 +010097 /* AHB: Internal USB Peripherals (USB, SATA) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098 tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
Stefan Roese41712b42008-03-05 12:31:53 +010099
Adam Grahamf09f09d2008-10-08 10:12:53 -0700100#if defined(CONFIG_RAPIDIO)
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100101 /* TLB-entries for RapidIO (SRIO) */
Adam Grahamf09f09d2008-10-08 10:12:53 -0700102 tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
103 0xD, AC_R|AC_W|SA_G|SA_I)
104 tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,
105 0xD, AC_R|AC_W|SA_G|SA_I)
106 tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR,
107 0xD, AC_R|AC_W|SA_G|SA_I)
108 tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K, 0x00100000,
109 0x4, AC_R|AC_W|SA_G|SA_I)
110#endif
111
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100112 tlbtab_end
113
114#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
115 /*
116 * For NAND booting the first TLB has to be reconfigured to full size
117 * and with caching disabled after running from RAM!
118 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
120#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100121#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
122
123 .globl reconfig_tlb0
124reconfig_tlb0:
125 sync
126 isync
127 addi r4,r0,0x0000 /* TLB entry #0 */
128 lis r5,TLB00@h
129 ori r5,r5,TLB00@l
130 tlbwe r5,r4,0x0000 /* Save it out */
131 lis r5,TLB01@h
132 ori r5,r5,TLB01@l
133 tlbwe r5,r4,0x0001 /* Save it out */
134 lis r5,TLB02@h
135 ori r5,r5,TLB02@l
136 tlbwe r5,r4,0x0002 /* Save it out */
137 sync
138 isync
139 blr
140#endif