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Bin Meng9c7dea62015-05-25 22:35:04 +08001/*
2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
Simon Glasse76187a2016-01-19 21:32:25 -07008#include <dm.h>
Bin Meng9c7dea62015-05-25 22:35:04 +08009#include <errno.h>
10#include <fdtdec.h>
11#include <malloc.h>
12#include <asm/io.h>
13#include <asm/irq.h>
14#include <asm/pci.h>
15#include <asm/pirq_routing.h>
Bin Meng10d569e2016-05-11 07:44:57 -070016#include <asm/tables.h>
Bin Meng9c7dea62015-05-25 22:35:04 +080017
18DECLARE_GLOBAL_DATA_PTR;
19
Bin Mengb46c2082016-02-01 01:40:51 -080020bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
Bin Meng9c7dea62015-05-25 22:35:04 +080021{
Bin Mengb46c2082016-02-01 01:40:51 -080022 struct irq_router *priv = dev_get_priv(dev);
Bin Meng9c7dea62015-05-25 22:35:04 +080023 u8 pirq;
Bin Mengb46c2082016-02-01 01:40:51 -080024 int base = priv->link_base;
Bin Meng9c7dea62015-05-25 22:35:04 +080025
Bin Mengb46c2082016-02-01 01:40:51 -080026 if (priv->config == PIRQ_VIA_PCI)
Bin Meng248c4fa2016-02-01 01:40:52 -080027 dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq);
Bin Meng9c7dea62015-05-25 22:35:04 +080028 else
Bin Mengb46c2082016-02-01 01:40:51 -080029 pirq = readb(priv->ibase + LINK_N2V(link, base));
Bin Meng9c7dea62015-05-25 22:35:04 +080030
31 pirq &= 0xf;
32
33 /* IRQ# 0/1/2/8/13 are reserved */
34 if (pirq < 3 || pirq == 8 || pirq == 13)
35 return false;
36
37 return pirq == irq ? true : false;
38}
39
Bin Mengb46c2082016-02-01 01:40:51 -080040int pirq_translate_link(struct udevice *dev, int link)
Bin Meng9c7dea62015-05-25 22:35:04 +080041{
Bin Mengb46c2082016-02-01 01:40:51 -080042 struct irq_router *priv = dev_get_priv(dev);
43
44 return LINK_V2N(link, priv->link_base);
Bin Meng9c7dea62015-05-25 22:35:04 +080045}
46
Bin Mengb46c2082016-02-01 01:40:51 -080047void pirq_assign_irq(struct udevice *dev, int link, u8 irq)
Bin Meng9c7dea62015-05-25 22:35:04 +080048{
Bin Mengb46c2082016-02-01 01:40:51 -080049 struct irq_router *priv = dev_get_priv(dev);
50 int base = priv->link_base;
Bin Meng9c7dea62015-05-25 22:35:04 +080051
52 /* IRQ# 0/1/2/8/13 are reserved */
53 if (irq < 3 || irq == 8 || irq == 13)
54 return;
55
Bin Mengb46c2082016-02-01 01:40:51 -080056 if (priv->config == PIRQ_VIA_PCI)
Bin Meng248c4fa2016-02-01 01:40:52 -080057 dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq);
Bin Meng9c7dea62015-05-25 22:35:04 +080058 else
Bin Mengb46c2082016-02-01 01:40:51 -080059 writeb(irq, priv->ibase + LINK_N2V(link, base));
Bin Meng9c7dea62015-05-25 22:35:04 +080060}
61
Bin Mengdf817492015-06-23 12:18:47 +080062static struct irq_info *check_dup_entry(struct irq_info *slot_base,
63 int entry_num, int bus, int device)
Bin Meng9c7dea62015-05-25 22:35:04 +080064{
Bin Mengdf817492015-06-23 12:18:47 +080065 struct irq_info *slot = slot_base;
66 int i;
Bin Meng9c7dea62015-05-25 22:35:04 +080067
Bin Mengdf817492015-06-23 12:18:47 +080068 for (i = 0; i < entry_num; i++) {
69 if (slot->bus == bus && slot->devfn == (device << 3))
70 break;
71 slot++;
72 }
73
74 return (i == entry_num) ? NULL : slot;
75}
76
Bin Mengb46c2082016-02-01 01:40:51 -080077static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot,
78 int bus, int device, int pin, int pirq)
Bin Mengdf817492015-06-23 12:18:47 +080079{
Bin Meng9c7dea62015-05-25 22:35:04 +080080 slot->bus = bus;
Bin Meng8c38e4d2015-06-23 12:18:46 +080081 slot->devfn = (device << 3) | 0;
Bin Mengb46c2082016-02-01 01:40:51 -080082 slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base);
83 slot->irq[pin - 1].bitmap = priv->irq_mask;
Bin Meng9c7dea62015-05-25 22:35:04 +080084}
85
Simon Glassb565d662016-01-19 21:32:28 -070086static int create_pirq_routing_table(struct udevice *dev)
Bin Meng9c7dea62015-05-25 22:35:04 +080087{
Bin Mengb46c2082016-02-01 01:40:51 -080088 struct irq_router *priv = dev_get_priv(dev);
Bin Meng9c7dea62015-05-25 22:35:04 +080089 const void *blob = gd->fdt_blob;
Bin Meng9c7dea62015-05-25 22:35:04 +080090 int node;
91 int len, count;
92 const u32 *cell;
93 struct irq_routing_table *rt;
Bin Mengdf817492015-06-23 12:18:47 +080094 struct irq_info *slot, *slot_base;
Bin Meng9c7dea62015-05-25 22:35:04 +080095 int irq_entries = 0;
96 int i;
97 int ret;
98
Simon Glassb565d662016-01-19 21:32:28 -070099 node = dev->of_offset;
Bin Meng9c7dea62015-05-25 22:35:04 +0800100
101 /* extract the bdf from fdt_pci_addr */
Bin Mengb46c2082016-02-01 01:40:51 -0800102 priv->bdf = dm_pci_get_bdf(dev->parent);
Bin Meng9c7dea62015-05-25 22:35:04 +0800103
Simon Glassb02e4042016-10-02 17:59:28 -0600104 ret = fdt_stringlist_search(blob, node, "intel,pirq-config", "pci");
Bin Meng9c7dea62015-05-25 22:35:04 +0800105 if (!ret) {
Bin Mengb46c2082016-02-01 01:40:51 -0800106 priv->config = PIRQ_VIA_PCI;
Bin Meng9c7dea62015-05-25 22:35:04 +0800107 } else {
Simon Glassb02e4042016-10-02 17:59:28 -0600108 ret = fdt_stringlist_search(blob, node, "intel,pirq-config",
109 "ibase");
Bin Meng9c7dea62015-05-25 22:35:04 +0800110 if (!ret)
Bin Mengb46c2082016-02-01 01:40:51 -0800111 priv->config = PIRQ_VIA_IBASE;
Bin Meng9c7dea62015-05-25 22:35:04 +0800112 else
113 return -EINVAL;
114 }
115
Simon Glass9e3ff9c2015-08-10 07:05:06 -0600116 ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1);
117 if (ret == -1)
Bin Meng9c7dea62015-05-25 22:35:04 +0800118 return ret;
Bin Mengb46c2082016-02-01 01:40:51 -0800119 priv->link_base = ret;
Bin Meng9c7dea62015-05-25 22:35:04 +0800120
Bin Mengb46c2082016-02-01 01:40:51 -0800121 priv->irq_mask = fdtdec_get_int(blob, node,
122 "intel,pirq-mask", PIRQ_BITMAP);
Bin Meng9c7dea62015-05-25 22:35:04 +0800123
Bin Meng07ac84e2016-05-07 07:46:13 -0700124 if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
125 /* Reserve IRQ9 for SCI */
126 priv->irq_mask &= ~(1 << 9);
127 }
128
Bin Mengb46c2082016-02-01 01:40:51 -0800129 if (priv->config == PIRQ_VIA_IBASE) {
Bin Meng9c7dea62015-05-25 22:35:04 +0800130 int ibase_off;
131
132 ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
133 if (!ibase_off)
134 return -EINVAL;
135
136 /*
137 * Here we assume that the IBASE register has already been
138 * properly configured by U-Boot before.
139 *
140 * By 'valid' we mean:
141 * 1) a valid memory space carved within system memory space
142 * assigned to IBASE register block.
143 * 2) memory range decoding is enabled.
144 * Hence we don't do any santify test here.
145 */
Bin Meng248c4fa2016-02-01 01:40:52 -0800146 dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase);
Bin Mengb46c2082016-02-01 01:40:51 -0800147 priv->ibase &= ~0xf;
Bin Meng9c7dea62015-05-25 22:35:04 +0800148 }
149
Bin Mengd4e61f52016-05-07 07:46:14 -0700150 priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
151 priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
152
Bin Meng9c7dea62015-05-25 22:35:04 +0800153 cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
Simon Glass9e3ff9c2015-08-10 07:05:06 -0600154 if (!cell || len % sizeof(struct pirq_routing))
Bin Meng9c7dea62015-05-25 22:35:04 +0800155 return -EINVAL;
Simon Glass9e3ff9c2015-08-10 07:05:06 -0600156 count = len / sizeof(struct pirq_routing);
Bin Meng9c7dea62015-05-25 22:35:04 +0800157
Simon Glass9e3ff9c2015-08-10 07:05:06 -0600158 rt = calloc(1, sizeof(struct irq_routing_table));
Bin Meng9c7dea62015-05-25 22:35:04 +0800159 if (!rt)
160 return -ENOMEM;
Bin Meng9c7dea62015-05-25 22:35:04 +0800161
162 /* Populate the PIRQ table fields */
163 rt->signature = PIRQ_SIGNATURE;
164 rt->version = PIRQ_VERSION;
Bin Mengb46c2082016-02-01 01:40:51 -0800165 rt->rtr_bus = PCI_BUS(priv->bdf);
166 rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf);
Bin Meng9c7dea62015-05-25 22:35:04 +0800167 rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
168 rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
169
Bin Mengdf817492015-06-23 12:18:47 +0800170 slot_base = rt->slots;
Bin Meng9c7dea62015-05-25 22:35:04 +0800171
172 /* Now fill in the irq_info entries in the PIRQ table */
Simon Glass9e3ff9c2015-08-10 07:05:06 -0600173 for (i = 0; i < count;
174 i++, cell += sizeof(struct pirq_routing) / sizeof(u32)) {
Bin Meng9c7dea62015-05-25 22:35:04 +0800175 struct pirq_routing pr;
176
177 pr.bdf = fdt_addr_to_cpu(cell[0]);
178 pr.pin = fdt_addr_to_cpu(cell[1]);
179 pr.pirq = fdt_addr_to_cpu(cell[2]);
180
181 debug("irq_info %d: b.d.f %x.%x.%x INT%c PIRQ%c\n",
182 i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
183 PCI_FUNC(pr.bdf), 'A' + pr.pin - 1,
184 'A' + pr.pirq);
Bin Mengdf817492015-06-23 12:18:47 +0800185
186 slot = check_dup_entry(slot_base, irq_entries,
187 PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
188 if (slot) {
189 debug("found entry for bus %d device %d, ",
190 PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
191
192 if (slot->irq[pr.pin - 1].link) {
193 debug("skipping\n");
194
195 /*
196 * Sanity test on the routed PIRQ pin
197 *
198 * If they don't match, show a warning to tell
199 * there might be something wrong with the PIRQ
200 * routing information in the device tree.
201 */
202 if (slot->irq[pr.pin - 1].link !=
Bin Mengb46c2082016-02-01 01:40:51 -0800203 LINK_N2V(pr.pirq, priv->link_base))
Bin Mengdf817492015-06-23 12:18:47 +0800204 debug("WARNING: Inconsistent PIRQ routing information\n");
Bin Mengdf817492015-06-23 12:18:47 +0800205 continue;
206 }
Simon Glass9e3ff9c2015-08-10 07:05:06 -0600207 } else {
208 slot = slot_base + irq_entries++;
Bin Mengdf817492015-06-23 12:18:47 +0800209 }
Simon Glass9e3ff9c2015-08-10 07:05:06 -0600210 debug("writing INT%c\n", 'A' + pr.pin - 1);
Bin Mengb46c2082016-02-01 01:40:51 -0800211 fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
212 pr.pin, pr.pirq);
Bin Meng9c7dea62015-05-25 22:35:04 +0800213 }
214
215 rt->size = irq_entries * sizeof(struct irq_info) + 32;
216
Bin Meng10d569e2016-05-11 07:44:57 -0700217 /* Fix up the table checksum */
218 rt->checksum = table_compute_checksum(rt, rt->size);
219
Simon Glass1bff8362017-01-16 07:04:16 -0700220 gd->arch.pirq_routing_table = rt;
Bin Meng9c7dea62015-05-25 22:35:04 +0800221
222 return 0;
223}
224
Bin Mengd4e61f52016-05-07 07:46:14 -0700225static void irq_enable_sci(struct udevice *dev)
226{
227 struct irq_router *priv = dev_get_priv(dev);
228
229 if (priv->actl_8bit) {
230 /* Bit7 must be turned on to enable ACPI */
231 dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
232 } else {
233 /* Write 0 to enable SCI on IRQ9 */
234 if (priv->config == PIRQ_VIA_PCI)
235 dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
236 else
237 writel(0, priv->ibase + priv->actl_addr);
238 }
239}
240
Simon Glassd3b884b2016-01-19 21:32:27 -0700241int irq_router_common_init(struct udevice *dev)
Simon Glasse76187a2016-01-19 21:32:25 -0700242{
Simon Glass7e4be122015-08-10 07:05:08 -0600243 int ret;
244
Simon Glassb565d662016-01-19 21:32:28 -0700245 ret = create_pirq_routing_table(dev);
Simon Glass7e4be122015-08-10 07:05:08 -0600246 if (ret) {
Bin Meng9c7dea62015-05-25 22:35:04 +0800247 debug("Failed to create pirq routing table\n");
Simon Glass7e4be122015-08-10 07:05:08 -0600248 return ret;
Bin Meng9c7dea62015-05-25 22:35:04 +0800249 }
Simon Glass7e4be122015-08-10 07:05:08 -0600250 /* Route PIRQ */
Simon Glass1bff8362017-01-16 07:04:16 -0700251 pirq_route_irqs(dev, gd->arch.pirq_routing_table->slots,
252 get_irq_slot_count(gd->arch.pirq_routing_table));
Simon Glass7e4be122015-08-10 07:05:08 -0600253
Bin Mengd4e61f52016-05-07 07:46:14 -0700254 if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
255 irq_enable_sci(dev);
256
Simon Glass7e4be122015-08-10 07:05:08 -0600257 return 0;
Bin Meng9c7dea62015-05-25 22:35:04 +0800258}
259
Simon Glassd3b884b2016-01-19 21:32:27 -0700260int irq_router_probe(struct udevice *dev)
261{
262 return irq_router_common_init(dev);
263}
264
Simon Glass42fd8c12017-01-16 07:03:35 -0700265ulong write_pirq_routing_table(ulong addr)
Bin Meng9c7dea62015-05-25 22:35:04 +0800266{
Simon Glass1bff8362017-01-16 07:04:16 -0700267 if (!gd->arch.pirq_routing_table)
Bin Meng67b24972015-05-25 22:35:07 +0800268 return addr;
269
Simon Glass1bff8362017-01-16 07:04:16 -0700270 return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table);
Bin Meng9c7dea62015-05-25 22:35:04 +0800271}
Simon Glasse76187a2016-01-19 21:32:25 -0700272
273static const struct udevice_id irq_router_ids[] = {
274 { .compatible = "intel,irq-router" },
275 { }
276};
277
278U_BOOT_DRIVER(irq_router_drv) = {
279 .name = "intel_irq",
280 .id = UCLASS_IRQ,
281 .of_match = irq_router_ids,
282 .probe = irq_router_probe,
Bin Mengb46c2082016-02-01 01:40:51 -0800283 .priv_auto_alloc_size = sizeof(struct irq_router),
Simon Glasse76187a2016-01-19 21:32:25 -0700284};
285
286UCLASS_DRIVER(irq) = {
287 .id = UCLASS_IRQ,
288 .name = "irq",
289};