blob: f6a1a61e61fece033c2ede4a8ad85f6c81bd3710 [file] [log] [blame]
Mingkai Hudd029362016-09-07 18:47:28 +08001/*
2 * Copyright 2016 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __CPLD_H__
8#define __CPLD_H__
9
10/*
11 * CPLD register set of LS1046ARDB board-specific.
12 * CPLD Revision: V2.1
13 */
14struct cpld_data {
15 u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
16 u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
17 u8 pcba_ver; /* 0x2 - PCBA Revision Register */
18 u8 system_rst; /* 0x3 - system reset register */
19 u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */
20 u8 cfg_rcw_src1; /* 0x5 - RCW Source Location POR Regsiter 1 */
21 u8 cfg_rcw_src2; /* 0x6 - RCW Source Location POR Regsiter 2 */
22 u8 vbank; /* 0x7 - QSPI Flash Bank Setting Register */
23 u8 sysclk_sel; /* 0x8 - System clock POR Register */
24 u8 uart_sel; /* 0x9 - UART1 Connection Control Register */
25 u8 sd1refclk_sel; /* 0xA - */
26 u8 rgmii_1588_sel; /* 0xB - */
27 u8 reg_1588_clk_sel; /* 0xC - */
28 u8 status_led; /* 0xD - */
29 u8 global_rst; /* 0xE - */
30 u8 sd_emmc; /* 0xF - SD/EMMC Interface Control Regsiter */
31 u8 vdd_en; /* 0x10 - VDD Voltage Control Enable Register */
32 u8 vdd_sel; /* 0x11 - VDD Voltage Control Register */
33};
34
35u8 cpld_read(unsigned int reg);
36void cpld_write(unsigned int reg, u8 value);
37void cpld_rev_bit(unsigned char *value);
Hou Zhiqiang64245772016-12-09 16:08:59 +080038void cpld_select_core_volt(bool en_0v9);
Mingkai Hudd029362016-09-07 18:47:28 +080039
40#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
41#define CPLD_WRITE(reg, value) \
42 cpld_write(offsetof(struct cpld_data, reg), value)
43
44/* CPLD on IFC */
45#define CPLD_SW_MUX_BANK_SEL 0x40
46#define CPLD_BANK_SEL_MASK 0x07
47#define CPLD_BANK_SEL_ALTBANK 0x04
48#define CPLD_CFG_RCW_SRC_QSPI 0x044
49#define CPLD_CFG_RCW_SRC_SD 0x040
50#endif