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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Nikita Kiryanovbaaa7dd2015-02-03 13:32:20 +02002/*
3 * atmel_lcd.h - Atmel LCD Controller structures
4 *
5 * (C) Copyright 2001
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Nikita Kiryanovbaaa7dd2015-02-03 13:32:20 +02007 */
8
9#ifndef _ATMEL_LCD_H_
10#define _ATMEL_LCD_H_
11
Tom Rini1e8ce112023-12-14 13:16:57 -050012#include <linux/types.h>
13
Simon Glass9dc89a02016-05-05 07:28:20 -060014/**
Simon Glass8a8d24b2020-12-03 16:55:23 -070015 * struct atmel_lcd_plat - platform data for Atmel LCDs with driver model
Simon Glass9dc89a02016-05-05 07:28:20 -060016 *
17 * @timing_index: Index of LCD timing to use in device tree node
18 */
Simon Glass8a8d24b2020-12-03 16:55:23 -070019struct atmel_lcd_plat {
Simon Glass9dc89a02016-05-05 07:28:20 -060020 int timing_index;
21};
22
Nikita Kiryanovbaaa7dd2015-02-03 13:32:20 +020023typedef struct vidinfo {
24 ushort vl_col; /* Number of columns (i.e. 640) */
25 ushort vl_row; /* Number of rows (i.e. 480) */
Hannes Petermaier604c7d42015-03-27 08:01:38 +010026 ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */
27 u_long vl_clk; /* pixel clock in ps */
Nikita Kiryanovbaaa7dd2015-02-03 13:32:20 +020028
29 /* LCD configuration register */
30 u_long vl_sync; /* Horizontal / vertical sync */
31 u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
32 u_long vl_tft; /* 0 = passive, 1 = TFT */
33 u_long vl_cont_pol_low; /* contrast polarity is low */
34 u_long vl_clk_pol; /* clock polarity */
35
36 /* Horizontal control register. */
37 u_long vl_hsync_len; /* Length of horizontal sync */
38 u_long vl_left_margin; /* Time from sync to picture */
39 u_long vl_right_margin; /* Time from picture to sync */
40
41 /* Vertical control register. */
42 u_long vl_vsync_len; /* Length of vertical sync */
43 u_long vl_upper_margin; /* Time from sync to picture */
44 u_long vl_lower_margin; /* Time from picture to sync */
45
46 u_long mmio; /* Memory mapped registers */
Wenyou Yangd330e042017-09-13 14:58:46 +080047
48 u_int logo_width;
49 u_int logo_height;
50 int logo_x_offset;
51 int logo_y_offset;
52 u_long logo_addr;
Nikita Kiryanovbaaa7dd2015-02-03 13:32:20 +020053} vidinfo_t;
54
Wenyou Yangd330e042017-09-13 14:58:46 +080055void atmel_logo_info(vidinfo_t *info);
56void microchip_logo_info(vidinfo_t *info);
57
Nikita Kiryanovbaaa7dd2015-02-03 13:32:20 +020058#endif