Simon Glass | 6caa195 | 2013-05-08 08:06:03 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013, Google Inc. |
| 3 | * |
| 4 | * Copyright (C) 2011 |
| 5 | * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> |
| 6 | * - Added prep subcommand support |
| 7 | * - Reorganized source - modeled after powerpc version |
| 8 | * |
| 9 | * (C) Copyright 2002 |
| 10 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 11 | * Marius Groeger <mgroeger@sysgo.de> |
| 12 | * |
| 13 | * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) |
| 14 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 15 | * SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | 6caa195 | 2013-05-08 08:06:03 +0000 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <common.h> |
| 19 | #include <fdt_support.h> |
Tom Rini | 4588d61 | 2015-05-14 11:07:03 -0400 | [diff] [blame] | 20 | #ifdef CONFIG_ARMV7_NONSEC |
Jan Kiszka | d6b72da | 2015-04-21 07:18:32 +0200 | [diff] [blame] | 21 | #include <asm/armv7.h> |
Tom Rini | 4588d61 | 2015-05-14 11:07:03 -0400 | [diff] [blame] | 22 | #endif |
Tom Rini | dd09f7e | 2015-03-05 20:19:36 -0500 | [diff] [blame] | 23 | #include <asm/psci.h> |
Masahiro Yamada | 6b6024e | 2016-06-27 19:31:05 +0900 | [diff] [blame] | 24 | #include <asm/spin_table.h> |
Simon Glass | 6caa195 | 2013-05-08 08:06:03 +0000 | [diff] [blame] | 25 | |
| 26 | DECLARE_GLOBAL_DATA_PTR; |
| 27 | |
Ma Haijun | e29607e | 2014-07-12 14:24:06 +0100 | [diff] [blame] | 28 | int arch_fixup_fdt(void *blob) |
Simon Glass | 6caa195 | 2013-05-08 08:06:03 +0000 | [diff] [blame] | 29 | { |
B, Ravi | 984a3c8 | 2017-04-18 17:27:26 +0530 | [diff] [blame] | 30 | int ret = 0; |
| 31 | #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_OF_LIBFDT) |
Simon Glass | 6caa195 | 2013-05-08 08:06:03 +0000 | [diff] [blame] | 32 | bd_t *bd = gd->bd; |
B, Ravi | 984a3c8 | 2017-04-18 17:27:26 +0530 | [diff] [blame] | 33 | int bank; |
Simon Glass | 6caa195 | 2013-05-08 08:06:03 +0000 | [diff] [blame] | 34 | u64 start[CONFIG_NR_DRAM_BANKS]; |
| 35 | u64 size[CONFIG_NR_DRAM_BANKS]; |
| 36 | |
| 37 | for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { |
| 38 | start[bank] = bd->bi_dram[bank].start; |
| 39 | size[bank] = bd->bi_dram[bank].size; |
Jan Kiszka | d6b72da | 2015-04-21 07:18:32 +0200 | [diff] [blame] | 40 | #ifdef CONFIG_ARMV7_NONSEC |
| 41 | ret = armv7_apply_memory_carveout(&start[bank], &size[bank]); |
| 42 | if (ret) |
| 43 | return ret; |
| 44 | #endif |
Simon Glass | 6caa195 | 2013-05-08 08:06:03 +0000 | [diff] [blame] | 45 | } |
| 46 | |
B, Ravi | 984a3c8 | 2017-04-18 17:27:26 +0530 | [diff] [blame] | 47 | #ifdef CONFIG_OF_LIBFDT |
Marc Zyngier | e771a3d | 2014-07-12 14:24:07 +0100 | [diff] [blame] | 48 | ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); |
Marc Zyngier | e771a3d | 2014-07-12 14:24:07 +0100 | [diff] [blame] | 49 | if (ret) |
| 50 | return ret; |
B, Ravi | 984a3c8 | 2017-04-18 17:27:26 +0530 | [diff] [blame] | 51 | #endif |
Marc Zyngier | e771a3d | 2014-07-12 14:24:07 +0100 | [diff] [blame] | 52 | |
Masahiro Yamada | 6b6024e | 2016-06-27 19:31:05 +0900 | [diff] [blame] | 53 | #ifdef CONFIG_ARMV8_SPIN_TABLE |
| 54 | ret = spin_table_update_dt(blob); |
| 55 | if (ret) |
| 56 | return ret; |
| 57 | #endif |
| 58 | |
macro.wave.z@gmail.com | 9a56175 | 2016-12-08 11:58:25 +0800 | [diff] [blame] | 59 | #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI) || \ |
Hou Zhiqiang | daa9264 | 2017-01-16 17:31:48 +0800 | [diff] [blame] | 60 | defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) |
Tom Rini | dd09f7e | 2015-03-05 20:19:36 -0500 | [diff] [blame] | 61 | ret = psci_update_dt(blob); |
Masahiro Yamada | 6441e3d | 2016-06-17 21:51:48 +0900 | [diff] [blame] | 62 | if (ret) |
| 63 | return ret; |
Marc Zyngier | e771a3d | 2014-07-12 14:24:07 +0100 | [diff] [blame] | 64 | #endif |
B, Ravi | 984a3c8 | 2017-04-18 17:27:26 +0530 | [diff] [blame] | 65 | #endif |
Masahiro Yamada | 6441e3d | 2016-06-17 21:51:48 +0900 | [diff] [blame] | 66 | |
| 67 | return 0; |
Simon Glass | 6caa195 | 2013-05-08 08:06:03 +0000 | [diff] [blame] | 68 | } |