blob: c1291007b37c2b12fff2cb1c5cf8739682e8d667 [file] [log] [blame]
Heiner Kallweita3b02a12017-04-12 20:28:36 +02001/*
2 * Copyright (c) 2016 Andreas Färber
3 *
4 * Copyright (c) 2016 BayLibre, SAS.
5 * Author: Neil Armstrong <narmstrong@baylibre.com>
6 *
7 * Copyright (c) 2016 Endless Computers, Inc.
8 * Author: Carlo Caione <carlo@endlessm.com>
9 *
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 * a) This library is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
19 *
20 * This library is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * Or, alternatively,
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
47 */
48
49#include <dt-bindings/gpio/gpio.h>
50#include <dt-bindings/interrupt-controller/irq.h>
51#include <dt-bindings/interrupt-controller/arm-gic.h>
52
53/ {
54 interrupt-parent = <&gic>;
55 #address-cells = <2>;
56 #size-cells = <2>;
57
58 reserved-memory {
59 #address-cells = <2>;
60 #size-cells = <2>;
61 ranges;
62
63 /* 16 MiB reserved for Hardware ROM Firmware */
64 hwrom_reserved: hwrom@0 {
65 reg = <0x0 0x0 0x0 0x1000000>;
66 no-map;
67 };
68
69 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
70 secmon_reserved: secmon@10000000 {
71 reg = <0x0 0x10000000 0x0 0x200000>;
72 no-map;
73 };
74 };
75
76 cpus {
77 #address-cells = <0x2>;
78 #size-cells = <0x0>;
79
80 cpu0: cpu@0 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a53", "arm,armv8";
83 reg = <0x0 0x0>;
84 enable-method = "psci";
85 next-level-cache = <&l2>;
86 clocks = <&scpi_dvfs 0>;
87 };
88
89 cpu1: cpu@1 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a53", "arm,armv8";
92 reg = <0x0 0x1>;
93 enable-method = "psci";
94 next-level-cache = <&l2>;
95 clocks = <&scpi_dvfs 0>;
96 };
97
98 cpu2: cpu@2 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a53", "arm,armv8";
101 reg = <0x0 0x2>;
102 enable-method = "psci";
103 next-level-cache = <&l2>;
104 clocks = <&scpi_dvfs 0>;
105 };
106
107 cpu3: cpu@3 {
108 device_type = "cpu";
109 compatible = "arm,cortex-a53", "arm,armv8";
110 reg = <0x0 0x3>;
111 enable-method = "psci";
112 next-level-cache = <&l2>;
113 clocks = <&scpi_dvfs 0>;
114 };
115
116 l2: l2-cache0 {
117 compatible = "cache";
118 };
119 };
120
121 arm-pmu {
122 compatible = "arm,cortex-a53-pmu";
123 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
127 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
128 };
129
130 psci {
131 compatible = "arm,psci-0.2";
132 method = "smc";
133 };
134
135 timer {
136 compatible = "arm,armv8-timer";
137 interrupts = <GIC_PPI 13
138 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
139 <GIC_PPI 14
140 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
141 <GIC_PPI 11
142 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
143 <GIC_PPI 10
144 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
145 };
146
147 xtal: xtal-clk {
148 compatible = "fixed-clock";
149 clock-frequency = <24000000>;
150 clock-output-names = "xtal";
151 #clock-cells = <0>;
152 };
153
154 firmware {
155 sm: secure-monitor {
156 compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
157 };
158 };
159
160 efuse: efuse {
161 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
162 #address-cells = <1>;
163 #size-cells = <1>;
164
165 sn: sn@14 {
166 reg = <0x14 0x10>;
167 };
168
169 eth_mac: eth_mac@34 {
170 reg = <0x34 0x10>;
171 };
172
173 bid: bid@46 {
174 reg = <0x46 0x30>;
175 };
176 };
177
178 scpi {
179 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
180 mboxes = <&mailbox 1 &mailbox 2>;
181 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
182
183 scpi_clocks: clocks {
184 compatible = "arm,scpi-clocks";
185
186 scpi_dvfs: scpi_clocks@0 {
187 compatible = "arm,scpi-dvfs-clocks";
188 #clock-cells = <1>;
189 clock-indices = <0>;
190 clock-output-names = "vcpu";
191 };
192 };
193
194 scpi_sensors: sensors {
195 compatible = "arm,scpi-sensors";
196 #thermal-sensor-cells = <1>;
197 };
198 };
199
200 soc {
201 compatible = "simple-bus";
202 #address-cells = <2>;
203 #size-cells = <2>;
204 ranges;
205
206 cbus: cbus@c1100000 {
207 compatible = "simple-bus";
208 reg = <0x0 0xc1100000 0x0 0x100000>;
209 #address-cells = <2>;
210 #size-cells = <2>;
211 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
212
213 reset: reset-controller@4404 {
214 compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
215 reg = <0x0 0x04404 0x0 0x20>;
216 #reset-cells = <1>;
217 };
218
219 uart_A: serial@84c0 {
220 compatible = "amlogic,meson-uart";
221 reg = <0x0 0x84c0 0x0 0x14>;
222 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
223 clocks = <&xtal>;
224 status = "disabled";
225 };
226
227 uart_B: serial@84dc {
228 compatible = "amlogic,meson-uart";
229 reg = <0x0 0x84dc 0x0 0x14>;
230 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
231 clocks = <&xtal>;
232 status = "disabled";
233 };
234
235 i2c_A: i2c@8500 {
236 compatible = "amlogic,meson-gxbb-i2c";
237 reg = <0x0 0x08500 0x0 0x20>;
238 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
239 #address-cells = <1>;
240 #size-cells = <0>;
241 status = "disabled";
242 };
243
244 pwm_ab: pwm@8550 {
245 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
246 reg = <0x0 0x08550 0x0 0x10>;
247 #pwm-cells = <3>;
248 status = "disabled";
249 };
250
251 pwm_cd: pwm@8650 {
252 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
253 reg = <0x0 0x08650 0x0 0x10>;
254 #pwm-cells = <3>;
255 status = "disabled";
256 };
257
258 pwm_ef: pwm@86c0 {
259 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
260 reg = <0x0 0x086c0 0x0 0x10>;
261 #pwm-cells = <3>;
262 status = "disabled";
263 };
264
265 uart_C: serial@8700 {
266 compatible = "amlogic,meson-uart";
267 reg = <0x0 0x8700 0x0 0x14>;
268 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
269 clocks = <&xtal>;
270 status = "disabled";
271 };
272
273 i2c_B: i2c@87c0 {
274 compatible = "amlogic,meson-gxbb-i2c";
275 reg = <0x0 0x087c0 0x0 0x20>;
276 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
277 #address-cells = <1>;
278 #size-cells = <0>;
279 status = "disabled";
280 };
281
282 i2c_C: i2c@87e0 {
283 compatible = "amlogic,meson-gxbb-i2c";
284 reg = <0x0 0x087e0 0x0 0x20>;
285 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
286 #address-cells = <1>;
287 #size-cells = <0>;
288 status = "disabled";
289 };
290
291 watchdog@98d0 {
292 compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
293 reg = <0x0 0x098d0 0x0 0x10>;
294 clocks = <&xtal>;
295 };
296 };
297
298 gic: interrupt-controller@c4301000 {
299 compatible = "arm,gic-400";
300 reg = <0x0 0xc4301000 0 0x1000>,
301 <0x0 0xc4302000 0 0x2000>,
302 <0x0 0xc4304000 0 0x2000>,
303 <0x0 0xc4306000 0 0x2000>;
304 interrupt-controller;
305 interrupts = <GIC_PPI 9
306 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
307 #interrupt-cells = <3>;
308 #address-cells = <0>;
309 };
310
311 sram: sram@c8000000 {
312 compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
313 reg = <0x0 0xc8000000 0x0 0x14000>;
314
315 #address-cells = <1>;
316 #size-cells = <1>;
317 ranges = <0 0x0 0xc8000000 0x14000>;
318
319 cpu_scp_lpri: scp-shmem@0 {
320 compatible = "amlogic,meson-gxbb-scp-shmem";
321 reg = <0x13000 0x400>;
322 };
323
324 cpu_scp_hpri: scp-shmem@200 {
325 compatible = "amlogic,meson-gxbb-scp-shmem";
326 reg = <0x13400 0x400>;
327 };
328 };
329
330 aobus: aobus@c8100000 {
331 compatible = "simple-bus";
332 reg = <0x0 0xc8100000 0x0 0x100000>;
333 #address-cells = <2>;
334 #size-cells = <2>;
335 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
336
337 uart_AO: serial@4c0 {
338 compatible = "amlogic,meson-uart";
339 reg = <0x0 0x004c0 0x0 0x14>;
340 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
341 clocks = <&xtal>;
342 status = "disabled";
343 };
344
345 uart_AO_B: serial@4e0 {
346 compatible = "amlogic,meson-uart";
347 reg = <0x0 0x004e0 0x0 0x14>;
348 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
349 clocks = <&xtal>;
350 status = "disabled";
351 };
352
353 ir: ir@580 {
354 compatible = "amlogic,meson-gxbb-ir";
355 reg = <0x0 0x00580 0x0 0x40>;
356 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
357 status = "disabled";
358 };
359 };
360
361 periphs: periphs@c8834000 {
362 compatible = "simple-bus";
363 reg = <0x0 0xc8834000 0x0 0x2000>;
364 #address-cells = <2>;
365 #size-cells = <2>;
366 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
367
368 rng {
369 compatible = "amlogic,meson-rng";
370 reg = <0x0 0x0 0x0 0x4>;
371 };
372 };
373
374
375 hiubus: hiubus@c883c000 {
376 compatible = "simple-bus";
377 reg = <0x0 0xc883c000 0x0 0x2000>;
378 #address-cells = <2>;
379 #size-cells = <2>;
380 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
381
382 mailbox: mailbox@404 {
383 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
384 reg = <0 0x404 0 0x4c>;
385 interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
386 <0 209 IRQ_TYPE_EDGE_RISING>,
387 <0 210 IRQ_TYPE_EDGE_RISING>;
388 #mbox-cells = <1>;
389 };
390 };
391
392 ethmac: ethernet@c9410000 {
393 compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
394 reg = <0x0 0xc9410000 0x0 0x10000
395 0x0 0xc8834540 0x0 0x4>;
396 interrupts = <0 8 1>;
397 interrupt-names = "macirq";
398 phy-mode = "rgmii";
399 status = "disabled";
400 };
401
402 apb: apb@d0000000 {
403 compatible = "simple-bus";
404 reg = <0x0 0xd0000000 0x0 0x200000>;
405 #address-cells = <2>;
406 #size-cells = <2>;
407 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
408
409 sd_emmc_a: mmc@70000 {
410 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
411 reg = <0x0 0x70000 0x0 0x2000>;
412 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
413 status = "disabled";
414 };
415
416 sd_emmc_b: mmc@72000 {
417 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
418 reg = <0x0 0x72000 0x0 0x2000>;
419 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
420 status = "disabled";
421 };
422
423 sd_emmc_c: mmc@74000 {
424 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
425 reg = <0x0 0x74000 0x0 0x2000>;
426 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
427 status = "disabled";
428 };
429 };
430
431 vpu: vpu@d0100000 {
432 compatible = "amlogic,meson-gx-vpu";
433 reg = <0x0 0xd0100000 0x0 0x100000>,
434 <0x0 0xc883c000 0x0 0x1000>,
435 <0x0 0xc8838000 0x0 0x1000>;
436 reg-names = "vpu", "hhi", "dmc";
437 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
438 #address-cells = <1>;
439 #size-cells = <0>;
440
441 /* CVBS VDAC output port */
442 cvbs_vdac_port: port@0 {
443 reg = <0>;
444 };
445 };
446 };
447};