blob: b48390ba98ad5e22d2bb55685ac2271f28bfb546 [file] [log] [blame]
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +01001/*
2 * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
3 *
4 * Developed for DENX Software Engineering GmbH
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#include <common.h>
25
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010026/* This test performs testing of FPGA SCRATCH register,
27 * gets FPGA version and run get_ram_size() on FPGA memory
28 */
29
30#include <post.h>
31
32#include <asm/io.h>
33
34DECLARE_GLOBAL_DATA_PTR;
35
36#define FPGA_SCRATCH_REG 0xC4000050
37#define FPGA_VERSION_REG 0xC4000040
38#define FPGA_RAM_START 0xC4200000
39#define FPGA_RAM_END 0xC4203FFF
Yuri Tikhonov603f1942008-02-04 17:09:55 +010040#define FPGA_STAT 0xC400000C
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010041
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010042#if CONFIG_POST & CFG_POST_BSPEC3
43
44static int one_scratch_test(uint value)
45{
46 uint read_value;
47 int ret = 0;
48
49 out_be32((void *)FPGA_SCRATCH_REG, value);
50 /* read other location (protect against data lines capacity) */
51 ret = in_be16((void *)FPGA_VERSION_REG);
52 /* verify test pattern */
53 read_value = in_be32((void *)FPGA_SCRATCH_REG);
54 if (read_value != value) {
55 post_log("FPGA SCRATCH test failed write %08X, read %08X\n",
56 value, read_value);
57 ret = 1;
58 }
59
60 return ret;
61}
62
63/* Verify FPGA, get version & memory size */
64int fpga_post_test(int flags)
65{
66 uint old_value;
67 ushort version;
68 uint read_value;
69 int ret = 0;
70
71 post_log("\n");
72 old_value = in_be32((void *)FPGA_SCRATCH_REG);
73
74 if (one_scratch_test(0x55555555))
75 ret = 1;
76 if (one_scratch_test(0xAAAAAAAA))
77 ret = 1;
78
79 out_be32((void *)FPGA_SCRATCH_REG, old_value);
80
81 version = in_be16((void *)FPGA_VERSION_REG);
82 post_log("FPGA : version %u.%u\n",
83 (version >> 8) & 0xFF, version & 0xFF);
84
Yuri Tikhonov603f1942008-02-04 17:09:55 +010085 /* Enable write to FPGA RAM */
86 out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000);
87
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010088 read_value = get_ram_size((void *)CFG_FPGA_BASE_1, 0x4000);
89 post_log("FPGA RAM size: %d bytes\n", read_value);
90
91 return ret;
92}
93
94#endif /* CONFIG_POST & CFG_POST_BSPEC3 */