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Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00001/*
2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
3 *
Tom Rini0b179982013-07-24 09:34:30 -04004 * SPDX-License-Identifier: GPL-2.0
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00005 */
6
7#include <common.h>
Gabor Juhosf1957492013-05-22 03:57:44 +00008#include <netdev.h>
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00009
Gabor Juhosfeaa6062013-05-22 03:57:42 +000010#include <asm/addrspace.h>
Gabor Juhos01564312013-05-22 03:57:38 +000011#include <asm/io.h>
12#include <asm/malta.h>
Gabor Juhosfeaa6062013-05-22 03:57:42 +000013#include <pci_gt64120.h>
Gabor Juhos01564312013-05-22 03:57:38 +000014
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000015phys_size_t initdram(int board_type)
16{
17 return CONFIG_SYS_MEM_SIZE;
18}
19
20int checkboard(void)
21{
22 puts("Board: MIPS Malta CoreLV (Qemu)\n");
23 return 0;
24}
Gabor Juhos01564312013-05-22 03:57:38 +000025
Gabor Juhosf1957492013-05-22 03:57:44 +000026int board_eth_init(bd_t *bis)
27{
28 return pci_eth_init(bis);
29}
30
Gabor Juhos01564312013-05-22 03:57:38 +000031void _machine_restart(void)
32{
33 void __iomem *reset_base;
34
35 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
36 __raw_writel(GORESET, reset_base);
37}
Gabor Juhosfeaa6062013-05-22 03:57:42 +000038
39void pci_init_board(void)
40{
41 set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE));
42
43 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
44 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
45 0x10000000, 0x10000000, 128 * 1024 * 1024,
46 0x00000000, 0x00000000, 0x20000);
47}