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Michal Simekf190eaf2018-03-28 15:55:27 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU111
4 *
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/phy/phy.h>
17
18/ {
19 model = "ZynqMP ZCU111 RevA";
20 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
21
22 aliases {
23 ethernet0 = &gem3;
24 gpio0 = &gpio;
25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 mmc0 = &sdhci1;
28 rtc0 = &rtc;
29 serial0 = &uart0;
30 serial1 = &dcc;
31 spi0 = &qspi;
32 usb0 = &usb0;
33 };
34
35 chosen {
36 bootargs = "earlycon";
37 stdout-path = "serial0:115200n8";
38 };
39
40 memory@0 {
41 device_type = "memory";
42 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
43 /* Another 4GB connected to PL */
44 };
45
46 gpio-keys {
47 compatible = "gpio-keys";
Michal Simekf190eaf2018-03-28 15:55:27 +020048 autorepeat;
49 sw19 {
50 label = "sw19";
51 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
52 linux,code = <KEY_DOWN>;
53 gpio-key,wakeup;
54 autorepeat;
55 };
56 };
57
58 leds {
59 compatible = "gpio-leds";
60 heartbeat_led {
61 label = "heartbeat";
62 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
63 linux,default-trigger = "heartbeat";
64 };
65 };
66};
67
68&dcc {
69 status = "okay";
70};
71
72&fpd_dma_chan1 {
73 status = "okay";
74};
75
76&fpd_dma_chan2 {
77 status = "okay";
78};
79
80&fpd_dma_chan3 {
81 status = "okay";
82};
83
84&fpd_dma_chan4 {
85 status = "okay";
86};
87
88&fpd_dma_chan5 {
89 status = "okay";
90};
91
92&fpd_dma_chan6 {
93 status = "okay";
94};
95
96&fpd_dma_chan7 {
97 status = "okay";
98};
99
100&fpd_dma_chan8 {
101 status = "okay";
102};
103
104&gem3 {
105 status = "okay";
106 phy-handle = <&phy0>;
107 phy-mode = "rgmii-id";
108 phy0: phy@c {
109 reg = <0xc>;
110 ti,rx-internal-delay = <0x8>;
111 ti,tx-internal-delay = <0xa>;
112 ti,fifo-depth = <0x1>;
113 };
114};
115
116&gpio {
117 status = "okay";
118};
119
120&gpu {
121 status = "okay";
122};
123
124&i2c0 {
125 status = "okay";
126 clock-frequency = <400000>;
127
128 tca6416_u22: gpio@20 {
129 compatible = "ti,tca6416";
130 reg = <0x20>;
131 gpio-controller; /* interrupt not connected */
132 #gpio-cells = <2>;
133 /*
134 * IRQ not connected
135 * Lines:
136 * 0 - MAX6643_OT_B
137 * 1 - MAX6643_FANFAIL_B
138 * 2 - MIO26_PMU_INPUT_LS
139 * 4 - SFP_SI5382_INT_ALM
140 * 5 - IIC_MUX_RESET_B
141 * 6 - GEM3_EXP_RESET_B
142 * 10 - FMCP_HSPC_PRSNT_M2C_B
143 * 11 - CLK_SPI_MUX_SEL0
144 * 12 - CLK_SPI_MUX_SEL1
145 * 16 - IRPS5401_ALERT_B
146 * 17 - INA226_PMBUS_ALERT
147 * 3, 7, 13-15 - not connected
148 */
149 };
150
151 i2c-mux@75 { /* u23 */
152 compatible = "nxp,pca9544";
153 #address-cells = <1>;
154 #size-cells = <0>;
155 reg = <0x75>;
156 i2c@0 {
157 #address-cells = <1>;
158 #size-cells = <0>;
159 reg = <0>;
160 /* PS_PMBUS */
161 /* PMBUS_ALERT done via pca9544 */
162 ina226@40 { /* u67 */
163 compatible = "ti,ina226";
164 reg = <0x40>;
165 shunt-resistor = <2000>;
166 };
167 ina226@41 { /* u59 */
168 compatible = "ti,ina226";
169 reg = <0x41>;
170 shunt-resistor = <5000>;
171 };
172 ina226@42 { /* u61 */
173 compatible = "ti,ina226";
174 reg = <0x42>;
175 shunt-resistor = <5000>;
176 };
177 ina226@43 { /* u60 */
178 compatible = "ti,ina226";
179 reg = <0x43>;
180 shunt-resistor = <5000>;
181 };
182 ina226@45 { /* u64 */
183 compatible = "ti,ina226";
184 reg = <0x45>;
185 shunt-resistor = <5000>;
186 };
187 ina226@46 { /* u69 */
188 compatible = "ti,ina226";
189 reg = <0x46>;
190 shunt-resistor = <2000>;
191 };
192 ina226@47 { /* u66 */
193 compatible = "ti,ina226";
194 reg = <0x47>;
195 shunt-resistor = <5000>;
196 };
197 ina226@48 { /* u65 */
198 compatible = "ti,ina226";
199 reg = <0x48>;
200 shunt-resistor = <5000>;
201 };
202 ina226@49 { /* u63 */
203 compatible = "ti,ina226";
204 reg = <0x49>;
205 shunt-resistor = <5000>;
206 };
207 ina226@4a { /* u3 */
208 compatible = "ti,ina226";
209 reg = <0x4a>;
210 shunt-resistor = <5000>;
211 };
212 ina226@4b { /* u71 */
213 compatible = "ti,ina226";
214 reg = <0x4b>;
215 shunt-resistor = <5000>;
216 };
217 ina226@4c { /* u77 */
218 compatible = "ti,ina226";
219 reg = <0x4c>;
220 shunt-resistor = <5000>;
221 };
222 ina226@4d { /* u73 */
223 compatible = "ti,ina226";
224 reg = <0x4d>;
225 shunt-resistor = <5000>;
226 };
227 ina226@4e { /* u79 */
228 compatible = "ti,ina226";
229 reg = <0x4e>;
230 shunt-resistor = <5000>;
231 };
232 };
233 i2c@1 {
234 #address-cells = <1>;
235 #size-cells = <0>;
236 reg = <1>;
237 /* NC */
238 };
239 i2c@2 {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 reg = <2>;
243 irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
244 #clock-cells = <0>;
245 compatible = "infineon,irps5401";
246 reg = <0x43>;
247 };
248 irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
249 #clock-cells = <0>;
250 compatible = "infineon,irps5401";
251 reg = <0x44>;
252 };
253 irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
254 #clock-cells = <0>;
255 compatible = "infineon,irps5401";
256 reg = <0x45>;
257 };
258 /* u68 IR38064 +0 */
259 /* u70 IR38060 +1 */
260 /* u74 IR38060 +2 */
261 /* u75 IR38060 +6 */
262 /* J19 header too */
263
264 };
265 i2c@3 {
266 #address-cells = <1>;
267 #size-cells = <0>;
268 reg = <3>;
269 /* SYSMON */
270 };
271 };
272};
273
274&i2c1 {
275 status = "okay";
276 clock-frequency = <400000>;
277
278 i2c-mux@74 { /* u26 */
279 compatible = "nxp,pca9548";
280 #address-cells = <1>;
281 #size-cells = <0>;
282 reg = <0x74>;
283 i2c@0 {
284 #address-cells = <1>;
285 #size-cells = <0>;
286 reg = <0>;
287 /*
288 * IIC_EEPROM 1kB memory which uses 256B blocks
289 * where every block has different address.
290 * 0 - 256B address 0x54
291 * 256B - 512B address 0x55
292 * 512B - 768B address 0x56
293 * 768B - 1024B address 0x57
294 */
295 eeprom: eeprom@54 { /* u88 */
296 compatible = "atmel,24c08";
297 reg = <0x54>;
298 };
299 };
300 i2c@1 {
301 #address-cells = <1>;
302 #size-cells = <0>;
303 reg = <1>;
304 si5341: clock-generator@36 { /* SI5341 - u46 */
305 compatible = "si5341";
306 reg = <0x36>;
307 };
308
309 };
310 i2c@2 {
311 #address-cells = <1>;
312 #size-cells = <0>;
313 reg = <2>;
314 si570_1: clock-generator@5d { /* USER SI570 - u47 */
315 #clock-cells = <0>;
316 compatible = "silabs,si570";
317 reg = <0x5d>;
318 temperature-stability = <50>;
319 factory-fout = <300000000>;
320 clock-frequency = <300000000>;
321 };
322 };
323 i2c@3 {
324 #address-cells = <1>;
325 #size-cells = <0>;
326 reg = <3>;
327 si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
328 #clock-cells = <0>;
329 compatible = "silabs,si570";
330 reg = <0x5d>;
331 temperature-stability = <50>;
332 factory-fout = <156250000>;
333 clock-frequency = <148500000>;
334 };
335 };
336 i2c@4 {
337 #address-cells = <1>;
338 #size-cells = <0>;
339 reg = <4>;
340 si5328: clock-generator@69 { /* SI5328 - u48 */
341 compatible = "silabs,si5328";
342 reg = <0x69>;
343 };
344 };
345 i2c@5 {
346 #address-cells = <1>;
347 #size-cells = <0>;
348 reg = <5>;
349 sc18is603@2f { /* sc18is602 - u93 */
350 compatible = "nxp,sc18is603";
351 reg = <0x2f>;
352 /* 4 gpios for CS not handled by driver */
353 /*
354 * USB2ANY cable or
355 * LMK04208 - u90 or
356 * LMX2594 - u102 or
357 * LMX2594 - u103 or
358 * LMX2594 - u104
359 */
360 };
361 };
362 i2c@6 {
363 #address-cells = <1>;
364 #size-cells = <0>;
365 reg = <6>;
366 /* FMC connector */
367 };
368 /* 7 NC */
369 };
370
371 i2c-mux@75 {
372 compatible = "nxp,pca9548"; /* u27 */
373 #address-cells = <1>;
374 #size-cells = <0>;
375 reg = <0x75>;
376
377 i2c@0 {
378 #address-cells = <1>;
379 #size-cells = <0>;
380 reg = <0>;
381 /* FMCP_HSPC_IIC */
382 };
383 i2c@1 {
384 #address-cells = <1>;
385 #size-cells = <0>;
386 reg = <1>;
387 /* NC */
388 };
389 i2c@2 {
390 #address-cells = <1>;
391 #size-cells = <0>;
392 reg = <2>;
393 /* SYSMON */
394 };
395 i2c@3 {
396 #address-cells = <1>;
397 #size-cells = <0>;
398 reg = <3>;
399 /* DDR4 SODIMM */
400 dev@19 { /* u-boot detection FIXME */
401 compatible = "xxx";
402 reg = <0x19>;
403 };
404 dev@30 { /* u-boot detection */
405 compatible = "xxx";
406 reg = <0x30>;
407 };
408 dev@35 { /* u-boot detection */
409 compatible = "xxx";
410 reg = <0x35>;
411 };
412 dev@36 { /* u-boot detection */
413 compatible = "xxx";
414 reg = <0x36>;
415 };
416 dev@51 { /* u-boot detection - maybe SPD */
417 compatible = "xxx";
418 reg = <0x51>;
419 };
420 };
421 i2c@4 {
422 #address-cells = <1>;
423 #size-cells = <0>;
424 reg = <4>;
425 /* SFP3 */
426 };
427 i2c@5 {
428 #address-cells = <1>;
429 #size-cells = <0>;
430 reg = <5>;
431 /* SFP2 */
432 };
433 i2c@6 {
434 #address-cells = <1>;
435 #size-cells = <0>;
436 reg = <6>;
437 /* SFP1 */
438 };
439 i2c@7 {
440 #address-cells = <1>;
441 #size-cells = <0>;
442 reg = <7>;
443 /* SFP0 */
444 };
445 };
446};
447
448&qspi {
449 status = "okay";
450 is-dual = <1>;
451 flash@0 {
Michal Simek0ed45f02018-07-26 12:43:42 +0200452 compatible = "m25p80", "spi-flash"; /* 32MB */
Michal Simekf190eaf2018-03-28 15:55:27 +0200453 #address-cells = <1>;
454 #size-cells = <1>;
455 reg = <0x0>;
456 spi-tx-bus-width = <1>;
457 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
458 spi-max-frequency = <108000000>; /* Based on DC1 spec */
459 partition@qspi-fsbl-uboot { /* for testing purpose */
460 label = "qspi-fsbl-uboot";
461 reg = <0x0 0x100000>;
462 };
463 partition@qspi-linux { /* for testing purpose */
464 label = "qspi-linux";
465 reg = <0x100000 0x500000>;
466 };
467 partition@qspi-device-tree { /* for testing purpose */
468 label = "qspi-device-tree";
469 reg = <0x600000 0x20000>;
470 };
471 partition@qspi-rootfs { /* for testing purpose */
472 label = "qspi-rootfs";
473 reg = <0x620000 0x5E0000>;
474 };
475 };
476};
477
478&rtc {
479 status = "okay";
480};
481
482&sata {
483 status = "okay";
484 /* SATA OOB timing settings */
485 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
486 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
487 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
488 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
489 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
490 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
491 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
492 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
493 phy-names = "sata-phy";
494 phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
495};
496
497/* SD1 with level shifter */
498&sdhci1 {
499 status = "okay";
500 no-1-8-v;
Michal Simekf0d56142018-04-04 14:08:24 +0200501 disable-wp;
Michal Simekf190eaf2018-03-28 15:55:27 +0200502 xlnx,mio_bank = <1>;
503};
504
505&serdes {
506 status = "okay";
507};
508
509&uart0 {
510 status = "okay";
511};
512
513/* ULPI SMSC USB3320 */
514&usb0 {
515 status = "okay";
516};
517
518&dwc3_0 {
519 status = "okay";
520 dr_mode = "host";
521 snps,usb3_lpm_capable;
522 phy-names = "usb3-phy";
523 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
524};