blob: d3c6f75a126820d439430018a591a61293e263a7 [file] [log] [blame]
Tom Rix23b80982009-09-27 11:10:09 -05001/*
2 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Tom Rix23b80982009-09-27 11:10:09 -05004 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
6 *
7 * (C) Copyright 2009
8 * Eric Benard <eric@eukrea.com>
9 *
10 * Configuration settings for the Eukrea CPU9260 board.
11 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020012 * SPDX-License-Identifier: GPL-2.0+
Tom Rix23b80982009-09-27 11:10:09 -050013 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
Eric Benardc2b2a072011-04-03 06:35:54 +000018/* to be removed once maemory-map.h is fixed */
19#define AT91_BASE_SYS 0xffffe800
20#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
Tom Rix23b80982009-09-27 11:10:09 -050021
Achim Ehrlich7c966a82010-02-24 10:29:16 +010022#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
Eric Benard95d50e52011-06-06 22:48:28 +000023#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
Tom Rix23b80982009-09-27 11:10:09 -050024
25#if defined(CONFIG_CPU9G20)
Eric Benardc2b2a072011-04-03 06:35:54 +000026#define CONFIG_AT91SAM9G20
Tom Rix23b80982009-09-27 11:10:09 -050027#elif defined(CONFIG_CPU9260)
Eric Benardc2b2a072011-04-03 06:35:54 +000028#define CONFIG_AT91SAM9260
Tom Rix23b80982009-09-27 11:10:09 -050029#else
30#error "Unknown board"
31#endif
32
Eric Benard95d50e52011-06-06 22:48:28 +000033#include <asm/arch/hardware.h>
34
Tom Rix23b80982009-09-27 11:10:09 -050035#define CONFIG_ARCH_CPU_INIT
Eric Benardc2b2a072011-04-03 06:35:54 +000036#define CONFIG_DISPLAY_CPUINFO
37#define CONFIG_BOARD_EARLY_INIT_F
Tom Rix23b80982009-09-27 11:10:09 -050038
Eric Benardc2b2a072011-04-03 06:35:54 +000039#define CONFIG_CMDLINE_TAG
40#define CONFIG_SETUP_MEMORY_TAGS
41#define CONFIG_INITRD_TAG
42
43#if defined(CONFIG_NANDBOOT)
44#define CONFIG_SKIP_LOWLEVEL_INIT
45#define CONFIG_SYS_TEXT_BASE 0x23f00000
46#else
47#define CONFIG_SYS_TEXT_BASE 0x00000000
48#endif
Tom Rix23b80982009-09-27 11:10:09 -050049
50/* clocks */
51#if defined(CONFIG_CPU9G20)
52#define MASTER_PLL_DIV 0x01
53#define MASTER_PLL_MUL 0x2B
54#elif defined(CONFIG_CPU9260)
55#define MASTER_PLL_DIV 0x09
56#define MASTER_PLL_MUL 0x61
57#endif
58
59/* CKGR_MOR - enable main osc. */
60#define CONFIG_SYS_MOR_VAL \
61 (AT91_PMC_MOSCEN | \
62 (255 << 8)) /* Main Oscillator Start-up Time */
63#if defined(CONFIG_CPU9G20)
64#define CONFIG_SYS_PLLAR_VAL \
65 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
66 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
67#elif defined(CONFIG_CPU9260)
68#define CONFIG_SYS_PLLAR_VAL \
69 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
70 AT91_PMC_OUT | \
71 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
72#endif
73
74#if defined(CONFIG_CPU9G20)
75#define CONFIG_SYS_MCKR1_VAL \
76 (AT91_PMC_CSS_PLLA | \
77 AT91_PMC_PRES_1 | \
78 AT91SAM9_PMC_MDIV_6 | \
79 AT91_PMC_PDIV_2)
80#define CONFIG_SYS_MCKR2_VAL \
81 CONFIG_SYS_MCKR1_VAL
82#elif defined(CONFIG_CPU9260)
83#define CONFIG_SYS_MCKR1_VAL \
84 (AT91_PMC_CSS_SLOW | \
85 AT91_PMC_PRES_1 | \
86 AT91SAM9_PMC_MDIV_2 | \
87 AT91_PMC_PDIV_1)
88#define CONFIG_SYS_MCKR2_VAL \
89 (AT91_PMC_CSS_PLLA | \
90 AT91_PMC_PRES_1 | \
91 AT91SAM9_PMC_MDIV_2 | \
92 AT91_PMC_PDIV_1)
93#endif
94
95/* define PDC[31:16] as DATA[31:16] */
96#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
97/* no pull-up for D[31:16] */
98#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
99
100/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
101#define CONFIG_SYS_MATRIX_EBICSA_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000102 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
103 AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
Tom Rix23b80982009-09-27 11:10:09 -0500104
105/* SDRAM */
106/* SDRAMC_MR Mode register */
107#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
108/* SDRAMC_TR - Refresh Timer register */
109#define CONFIG_SYS_SDRC_TR_VAL1 0x287
110/* SDRAMC_CR - Configuration register*/
111#if defined(CONFIG_CPU9G20)
112#define CONFIG_SYS_SDRC_CR_VAL_64MB \
113 (AT91_SDRAMC_NC_9 | \
114 AT91_SDRAMC_NR_13 | \
115 AT91_SDRAMC_NB_4 | \
116 AT91_SDRAMC_CAS_2 | \
117 AT91_SDRAMC_DBW_32 | \
118 (2 << 8) | /* Write Recovery Delay */ \
119 (9 << 12) | /* Row Cycle Delay */ \
120 (3 << 16) | /* Row Precharge Delay */ \
121 (3 << 20) | /* Row to Column Delay */ \
122 (6 << 24) | /* Active to Precharge Delay */ \
123 (10 << 28)) /* Exit Self Refresh to Active Delay */
124
125#define CONFIG_SYS_SDRC_CR_VAL_128MB \
126 (AT91_SDRAMC_NC_10 | \
127 AT91_SDRAMC_NR_13 | \
128 AT91_SDRAMC_NB_4 | \
129 AT91_SDRAMC_CAS_2 | \
130 AT91_SDRAMC_DBW_32 | \
131 (2 << 8) | /* Write Recovery Delay */ \
132 (9 << 12) | /* Row Cycle Delay */ \
133 (3 << 16) | /* Row Precharge Delay */ \
134 (3 << 20) | /* Row to Column Delay */ \
135 (6 << 24) | /* Active to Precharge Delay */ \
136 (10 << 28)) /* Exit Self Refresh to Active Delay */
137#elif defined(CONFIG_CPU9260)
138#define CONFIG_SYS_SDRC_CR_VAL_64MB \
139 (AT91_SDRAMC_NC_9 | \
140 AT91_SDRAMC_NR_13 | \
141 AT91_SDRAMC_NB_4 | \
142 AT91_SDRAMC_CAS_2 | \
143 AT91_SDRAMC_DBW_32 | \
144 (2 << 8) | /* Write Recovery Delay */ \
145 (7 << 12) | /* Row Cycle Delay */ \
146 (2 << 16) | /* Row Precharge Delay */ \
147 (2 << 20) | /* Row to Column Delay */ \
148 (5 << 24) | /* Active to Precharge Delay */ \
149 (8 << 28)) /* Exit Self Refresh to Active Delay */
150
151#define CONFIG_SYS_SDRC_CR_VAL_128MB \
152 (AT91_SDRAMC_NC_10 | \
153 AT91_SDRAMC_NR_13 | \
154 AT91_SDRAMC_NB_4 | \
155 AT91_SDRAMC_CAS_2 | \
156 AT91_SDRAMC_DBW_32 | \
157 (2 << 8) | /* Write Recovery Delay */ \
158 (7 << 12) | /* Row Cycle Delay */ \
159 (2 << 16) | /* Row Precharge Delay */ \
160 (2 << 20) | /* Row to Column Delay */ \
161 (5 << 24) | /* Active to Precharge Delay */ \
162 (8 << 28)) /* Exit Self Refresh to Active Delay */
163#endif
164
165/* Memory Device Register -> SDRAM */
166#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
167#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
168#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
169#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
170#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
171#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
172#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
173#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
174#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
175#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
176#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
177#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
178#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
179#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
180#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
181#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
182#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
183#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
184
185/* setup SMC0, CS0 (NOR Flash) - 16-bit */
186#if defined(CONFIG_CPU9G20)
187#define CONFIG_SYS_SMC0_SETUP0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000188 (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
189 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
Tom Rix23b80982009-09-27 11:10:09 -0500190#define CONFIG_SYS_SMC0_PULSE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000191 (AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) | \
192 AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
Tom Rix23b80982009-09-27 11:10:09 -0500193#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000194 (AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
Tom Rix23b80982009-09-27 11:10:09 -0500195#define CONFIG_SYS_SMC0_MODE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000196 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
197 AT91_SMC_MODE_DBW_16 | \
198 AT91_SMC_MODE_TDF | \
199 AT91_SMC_MODE_TDF_CYCLE(3))
Tom Rix23b80982009-09-27 11:10:09 -0500200#elif defined(CONFIG_CPU9260)
201#define CONFIG_SYS_SMC0_SETUP0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000202 (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
203 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
Tom Rix23b80982009-09-27 11:10:09 -0500204#define CONFIG_SYS_SMC0_PULSE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000205 (AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) | \
206 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
Tom Rix23b80982009-09-27 11:10:09 -0500207#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000208 (AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
Tom Rix23b80982009-09-27 11:10:09 -0500209#define CONFIG_SYS_SMC0_MODE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000210 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
211 AT91_SMC_MODE_DBW_16 | \
212 AT91_SMC_MODE_TDF | \
213 AT91_SMC_MODE_TDF_CYCLE(2))
Tom Rix23b80982009-09-27 11:10:09 -0500214#endif
215
216/* user reset enable */
217#define CONFIG_SYS_RSTC_RMR_VAL \
218 (AT91_RSTC_KEY | \
Eric Benardc2b2a072011-04-03 06:35:54 +0000219 AT91_RSTC_CR_PROCRST | \
220 AT91_RSTC_MR_ERSTL(1) | \
221 AT91_RSTC_MR_ERSTL(2))
Tom Rix23b80982009-09-27 11:10:09 -0500222
223/* Disable Watchdog */
224#define CONFIG_SYS_WDTC_WDMR_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000225 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
226 AT91_WDT_MR_WDV(0xfff) | \
227 AT91_WDT_MR_WDDIS | \
228 AT91_WDT_MR_WDD(0xfff))
Tom Rix23b80982009-09-27 11:10:09 -0500229
230/*
231 * Hardware drivers
232 */
Eric Benardc2b2a072011-04-03 06:35:54 +0000233#define CONFIG_AT91SAM9_WATCHDOG
234#define CONFIG_AT91_GPIO
235#define CONFIG_ATMEL_USART
Eric Benard95d50e52011-06-06 22:48:28 +0000236#define CONFIG_USART_BASE ATMEL_BASE_DBGU
237#define CONFIG_USART_ID ATMEL_ID_SYS
Tom Rix23b80982009-09-27 11:10:09 -0500238
239#define CONFIG_BOOTDELAY 3
240
241/*
242 * BOOTP options
243 */
Eric Benardc2b2a072011-04-03 06:35:54 +0000244#define CONFIG_BOOTP_BOOTFILESIZE
245#define CONFIG_BOOTP_BOOTPATH
246#define CONFIG_BOOTP_GATEWAY
247#define CONFIG_BOOTP_HOSTNAME
Tom Rix23b80982009-09-27 11:10:09 -0500248
249/*
250 * Command line configuration.
251 */
Eric Benardc2b2a072011-04-03 06:35:54 +0000252#define CONFIG_CMD_PING
253#define CONFIG_CMD_DHCP
254#define CONFIG_CMD_NAND
255#define CONFIG_CMD_USB
256#define CONFIG_CMD_FAT
257#define CONFIG_CMD_MII
Tom Rix23b80982009-09-27 11:10:09 -0500258
259/* SDRAM */
260#define CONFIG_NR_DRAM_BANKS 1
Eric Benardc2b2a072011-04-03 06:35:54 +0000261#define CONFIG_SYS_SDRAM_BASE 0x20000000
Tom Rix23b80982009-09-27 11:10:09 -0500262#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
Eric Benardc2b2a072011-04-03 06:35:54 +0000263#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
Tom Rix23b80982009-09-27 11:10:09 -0500264#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
265#else
Eric Benardc2b2a072011-04-03 06:35:54 +0000266#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
Tom Rix23b80982009-09-27 11:10:09 -0500267#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
268#endif
269
270/* NAND flash */
Eric Benardc2b2a072011-04-03 06:35:54 +0000271#define CONFIG_NAND_ATMEL
Tom Rix23b80982009-09-27 11:10:09 -0500272#define CONFIG_SYS_MAX_NAND_DEVICE 1
273#define CONFIG_SYS_NAND_BASE 0x40000000
274#define CONFIG_SYS_NAND_DBW_8 1
Andreas Bießmannac45bb12013-11-29 12:13:45 +0100275#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PC(13)
276#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
Tom Rix23b80982009-09-27 11:10:09 -0500277#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
278#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Tom Rix23b80982009-09-27 11:10:09 -0500279
280/* NOR flash */
Eric Benardc2b2a072011-04-03 06:35:54 +0000281#if defined(CONFIG_NANDBOOT)
282#define CONFIG_SYS_NO_FLASH
283#else
284#define CONFIG_SYS_FLASH_CFI
285#define CONFIG_FLASH_CFI_DRIVER
Tom Rix23b80982009-09-27 11:10:09 -0500286#define PHYS_FLASH_1 0x10000000
287#define PHYS_FLASH_2 0x12000000
288#define CONFIG_SYS_FLASH_BANKS_LIST \
289 { PHYS_FLASH_1, PHYS_FLASH_2 }
290#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
291#define CONFIG_SYS_MAX_FLASH_SECT (255+4)
292#define CONFIG_SYS_MAX_FLASH_BANKS 2
293#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Eric Benardc2b2a072011-04-03 06:35:54 +0000294#define CONFIG_SYS_FLASH_EMPTY_INFO
295#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
296#define CONFIG_SYS_FLASH_PROTECTION
Tom Rix23b80982009-09-27 11:10:09 -0500297#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
Eric Benardc2b2a072011-04-03 06:35:54 +0000298#endif
Tom Rix23b80982009-09-27 11:10:09 -0500299
300/* Ethernet */
Eric Benardc2b2a072011-04-03 06:35:54 +0000301#define CONFIG_MACB
302#define CONFIG_RMII
Tom Rix23b80982009-09-27 11:10:09 -0500303#define CONFIG_NET_RETRY_COUNT 20
Eric Benardc2b2a072011-04-03 06:35:54 +0000304#define CONFIG_MACB_SEARCH_PHY
Heiko Schocher4535a242013-11-18 08:07:23 +0100305#define CONFIG_AT91_WANTS_COMMON_PHY
Tom Rix23b80982009-09-27 11:10:09 -0500306
307/* LEDS */
308/* Status LED */
Eric Benardc2b2a072011-04-03 06:35:54 +0000309#define CONFIG_STATUS_LED
310#define CONFIG_BOARD_SPECIFIC_LED
Tom Rix23b80982009-09-27 11:10:09 -0500311#define STATUS_LED_RED 0
312#define STATUS_LED_GREEN 1
313#define STATUS_LED_YELLOW 2
314#define STATUS_LED_BLUE 3
315/* Red */
316#define STATUS_LED_BIT STATUS_LED_RED
317#define STATUS_LED_STATE STATUS_LED_OFF
318#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
319/* Green */
320#define STATUS_LED_BIT1 STATUS_LED_GREEN
321#define STATUS_LED_STATE1 STATUS_LED_OFF
322#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
323/* Yellow */
324#define STATUS_LED_BIT2 STATUS_LED_YELLOW
325#define STATUS_LED_STATE2 STATUS_LED_OFF
326#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
327/* Blue */
328#define STATUS_LED_BIT3 STATUS_LED_BLUE
329#define STATUS_LED_STATE3 STATUS_LED_ON
330#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
331/* Optional value */
332#define STATUS_LED_BOOT STATUS_LED_BIT
333
Eric Benardc2b2a072011-04-03 06:35:54 +0000334#define CONFIG_RED_LED AT91_PIO_PORTC, 11
335#define CONFIG_GREEN_LED AT91_PIO_PORTC, 12
336#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 7
337#define CONFIG_BLUE_LED AT91_PIO_PORTC, 9
Tom Rix23b80982009-09-27 11:10:09 -0500338
339/* USB */
Eric Benardc2b2a072011-04-03 06:35:54 +0000340#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800341#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Eric Benardc2b2a072011-04-03 06:35:54 +0000342#define CONFIG_USB_OHCI_NEW
343#define CONFIG_DOS_PARTITION
344#define CONFIG_SYS_USB_OHCI_CPU_INIT
Tom Rix23b80982009-09-27 11:10:09 -0500345#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
Eric Benardc2b2a072011-04-03 06:35:54 +0000346#if defined(CONFIG_CPU9G20)
347#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20"
348#elif defined(CONFIG_CPU9260)
Tom Rix23b80982009-09-27 11:10:09 -0500349#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
Eric Benardc2b2a072011-04-03 06:35:54 +0000350#endif
Tom Rix23b80982009-09-27 11:10:09 -0500351#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Eric Benardc2b2a072011-04-03 06:35:54 +0000352#define CONFIG_USB_STORAGE
Tom Rix23b80982009-09-27 11:10:09 -0500353
354#define CONFIG_SYS_LOAD_ADDR 0x21000000
Eric Benardc2b2a072011-04-03 06:35:54 +0000355#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
Tom Rix23b80982009-09-27 11:10:09 -0500356
Eric Benardc2b2a072011-04-03 06:35:54 +0000357#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
358#define CONFIG_SYS_MEMTEST_END \
359 (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
Tom Rix23b80982009-09-27 11:10:09 -0500360
Eric Benardc2b2a072011-04-03 06:35:54 +0000361#if defined(CONFIG_NANDBOOT)
362#define CONFIG_SYS_USE_NANDFLASH
363#undef CONFIG_SYS_USE_FLASH
364#else
365#define CONFIG_SYS_USE_FLASH
Tom Rix23b80982009-09-27 11:10:09 -0500366#undef CONFIG_SYS_USE_NANDFLASH
Eric Benardc2b2a072011-04-03 06:35:54 +0000367#endif
368
369#if defined(CONFIG_CPU9G20)
370#define CONFIG_SYS_BASEDIR "cpu9G20"
371#elif defined(CONFIG_CPU9260)
372#define CONFIG_SYS_BASEDIR "cpu9260"
373#endif
Tom Rix23b80982009-09-27 11:10:09 -0500374
375#if defined(CONFIG_SYS_USE_FLASH)
Eric Benardc2b2a072011-04-03 06:35:54 +0000376#define CONFIG_ENV_IS_IN_FLASH
Tom Rix23b80982009-09-27 11:10:09 -0500377#define CONFIG_ENV_OFFSET 0x40000
378#define CONFIG_ENV_SECT_SIZE 0x20000
379#define CONFIG_ENV_SIZE 0x20000
Eric Benardc2b2a072011-04-03 06:35:54 +0000380#define CONFIG_ENV_OVERWRITE
Tom Rix23b80982009-09-27 11:10:09 -0500381
382#define CONFIG_BOOTCOMMAND "run flashboot"
383
Eric Benardc2b2a072011-04-03 06:35:54 +0000384#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
Tom Rix23b80982009-09-27 11:10:09 -0500385#define MTDPARTS_DEFAULT \
386 "mtdparts=physmap-flash.0:" \
387 "256k(u-boot)ro," \
388 "128k(u-boot-env)ro," \
389 "1792k(kernel)," \
390 "-(rootfs);" \
391 "atmel_nand:-(nand)"
392
393#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
394
Tom Rix23b80982009-09-27 11:10:09 -0500395#define CONFIG_EXTRA_ENV_SETTINGS \
396 "mtdids=" MTDIDS_DEFAULT "\0" \
397 "mtdparts=" MTDPARTS_DEFAULT "\0" \
398 "partition=nand0,0\0" \
399 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
Eric Benardc2b2a072011-04-03 06:35:54 +0000400 "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
Tom Rix23b80982009-09-27 11:10:09 -0500401 "run ramargs;bootm 22000000\0" \
402 "flashboot=run ramargs;bootm 0x10060000\0" \
403 "basedir=" CONFIG_SYS_BASEDIR "\0" \
404 "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
405 "off 0x10000000 0x1003ffff;erase 0x10000000 " \
406 "0x1003ffff;cp.b 0x24000000 0x10000000 " \
407 "$(filesize)\0" \
408 "updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \
409 " 0x10060000 0x1021ffff;erase 0x10060000 " \
410 "0x1021ffff;cp.b 0x24000000 0x10060000 " \
411 "$(filesize)\0" \
412 "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \
413 "protect off 0x10220000 0x13ffffff;erase " \
414 "0x10220000 0x13ffffff;cp.b 0x24000000 " \
415 "0x10220000 $(filesize)\0" \
416 ""
Eric Benardc2b2a072011-04-03 06:35:54 +0000417#elif defined(CONFIG_NANDBOOT)
418#define CONFIG_ENV_IS_IN_NAND
419#define CONFIG_ENV_OFFSET 0x60000
420#define CONFIG_ENV_OFFSET_REDUND 0x80000
421#define CONFIG_ENV_SECT_SIZE 0x20000
422#define CONFIG_ENV_SIZE 0x20000
423#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
424#define CONFIG_ENV_OVERWRITE
425
426#define CONFIG_BOOTCOMMAND "run flashboot"
427
428#define MTDIDS_DEFAULT "nand0=atmel_nand"
429#define MTDPARTS_DEFAULT \
430 "mtdparts=atmel_nand:" \
431 "128k(bootstrap)ro," \
432 "256k(u-boot)ro," \
433 "128k(u-boot-env)ro," \
434 "128k(u-boot-env2)ro," \
435 "2M(kernel)," \
436 "-(rootfs)"
437
438#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs " \
439 "ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"
440
441#define CONFIG_EXTRA_ENV_SETTINGS \
442 "mtdids=" MTDIDS_DEFAULT "\0" \
443 "mtdparts=" MTDPARTS_DEFAULT "\0" \
444 "partition=nand0,5\0" \
445 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
446 "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
447 "run ramargs;bootm 22000000\0" \
448 "flashboot=run ramargs; nand read 0x22000000 0xA0000 " \
449 "0x200000; bootm 0x22000000\0" \
450 "basedir=" CONFIG_SYS_BASEDIR "\0" \
451 "u-boot=u-boot-eukrea-cpu9260.bin\0" \
452 "kernel=uImage-eukrea-cpu9260.bin\0" \
453 "rootfs=image-eukrea-cpu9260.ubi\0" \
454 "updtub=tftp ${loadaddr} $(basedir)/${u-boot}; " \
455 "nand erase 20000 40000; " \
456 "nand write ${loadaddr} 20000 40000\0" \
457 "updtui=tftp ${loadaddr} $(basedir)/${kernel}; " \
458 "nand erase a0000 200000; " \
459 "nand write ${loadaddr} a0000 200000\0" \
460 "updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; " \
461 "nand erase 2a0000 fd60000; " \
462 "nand write ${loadaddr} 2a0000 ${filesize}\0"
Tom Rix23b80982009-09-27 11:10:09 -0500463#endif
464
465#define CONFIG_BAUDRATE 115200
Tom Rix23b80982009-09-27 11:10:09 -0500466
467#if defined(CONFIG_CPU9G20)
468#define CONFIG_SYS_PROMPT "CPU9G20=> "
469#elif defined(CONFIG_CPU9260)
470#define CONFIG_SYS_PROMPT "CPU9260=> "
471#endif
472#define CONFIG_SYS_CBSIZE 256
473#define CONFIG_SYS_MAXARGS 16
474#define CONFIG_SYS_PBSIZE \
475 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Eric Benardc2b2a072011-04-03 06:35:54 +0000476#define CONFIG_SYS_LONGHELP
477#define CONFIG_CMDLINE_EDITING
478#define CONFIG_SILENT_CONSOLE
479#define CONFIG_NETCONSOLE
Tom Rix23b80982009-09-27 11:10:09 -0500480
481/*
482 * Size of malloc() pool
483 */
484#define CONFIG_SYS_MALLOC_LEN \
485 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
Tom Rix23b80982009-09-27 11:10:09 -0500486
Eric Benardc2b2a072011-04-03 06:35:54 +0000487#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
488 GENERATED_GBL_DATA_SIZE)
489
Tom Rix23b80982009-09-27 11:10:09 -0500490#endif