wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1 | /* |
| 2 | * tsec.c |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 3 | * Freescale Three Speed Ethernet Controller driver |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 4 | * |
| 5 | * This software may be used and distributed according to the |
| 6 | * terms of the GNU Public License, Version 2, incorporated |
| 7 | * herein by reference. |
| 8 | * |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 9 | * Copyright 2004 Freescale Semiconductor. |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 10 | * (C) Copyright 2003, Motorola, Inc. |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 11 | * maintained by Jon Loeliger (loeliger@freescale.com) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 12 | * author Andy Fleming |
| 13 | * |
| 14 | */ |
| 15 | |
| 16 | #include <config.h> |
| 17 | #include <mpc85xx.h> |
| 18 | #include <common.h> |
| 19 | #include <malloc.h> |
| 20 | #include <net.h> |
| 21 | #include <command.h> |
| 22 | |
| 23 | #if defined(CONFIG_TSEC_ENET) |
| 24 | #include "tsec.h" |
| 25 | |
| 26 | #define TX_BUF_CNT 2 |
| 27 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 28 | static uint rxIdx; /* index of the current RX buffer */ |
| 29 | static uint txIdx; /* index of the current TX buffer */ |
| 30 | |
| 31 | typedef volatile struct rtxbd { |
| 32 | txbd8_t txbd[TX_BUF_CNT]; |
| 33 | rxbd8_t rxbd[PKTBUFSRX]; |
| 34 | } RTXBD; |
| 35 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 36 | struct tsec_info_struct { |
| 37 | unsigned int phyaddr; |
| 38 | unsigned int gigabit; |
| 39 | unsigned int phyregidx; |
| 40 | }; |
| 41 | |
| 42 | |
| 43 | /* The tsec_info structure contains 3 values which the |
| 44 | * driver uses to determine how to operate a given ethernet |
| 45 | * device. For now, the structure is initialized with the |
| 46 | * knowledge that all current implementations have 2 TSEC |
| 47 | * devices, and one FEC. The information needed is: |
| 48 | * phyaddr - The address of the PHY which is attached to |
wdenk | 9d46ea4 | 2005-03-14 23:56:42 +0000 | [diff] [blame] | 49 | * the given device. |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 50 | * |
| 51 | * gigabit - This variable indicates whether the device |
wdenk | 9d46ea4 | 2005-03-14 23:56:42 +0000 | [diff] [blame] | 52 | * supports gigabit speed ethernet |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 53 | * |
| 54 | * phyregidx - This variable specifies which ethernet device |
wdenk | 9d46ea4 | 2005-03-14 23:56:42 +0000 | [diff] [blame] | 55 | * controls the MII Management registers which are connected |
| 56 | * to the PHY. For 8540/8560, only TSEC1 (index 0) has |
| 57 | * access to the PHYs, so all of the entries have "0". |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 58 | * |
| 59 | * The values specified in the table are taken from the board's |
| 60 | * config file in include/configs/. When implementing a new |
| 61 | * board with ethernet capability, it is necessary to define: |
| 62 | * TSEC1_PHY_ADDR |
| 63 | * TSEC1_PHYIDX |
| 64 | * TSEC2_PHY_ADDR |
| 65 | * TSEC2_PHYIDX |
| 66 | * |
| 67 | * and for 8560: |
| 68 | * FEC_PHY_ADDR |
| 69 | * FEC_PHYIDX |
| 70 | */ |
| 71 | static struct tsec_info_struct tsec_info[] = { |
| 72 | #ifdef CONFIG_MPC85XX_TSEC1 |
| 73 | {TSEC1_PHY_ADDR, 1, TSEC1_PHYIDX}, |
wdenk | 9d46ea4 | 2005-03-14 23:56:42 +0000 | [diff] [blame] | 74 | #else |
| 75 | { 0, 0, 0}, |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 76 | #endif |
| 77 | #ifdef CONFIG_MPC85XX_TSEC2 |
| 78 | {TSEC2_PHY_ADDR, 1, TSEC2_PHYIDX}, |
wdenk | 9d46ea4 | 2005-03-14 23:56:42 +0000 | [diff] [blame] | 79 | #else |
| 80 | { 0, 0, 0}, |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 81 | #endif |
| 82 | #ifdef CONFIG_MPC85XX_FEC |
| 83 | {FEC_PHY_ADDR, 0, FEC_PHYIDX}, |
wdenk | 9d46ea4 | 2005-03-14 23:56:42 +0000 | [diff] [blame] | 84 | #else |
| 85 | { 0, 0, 0}, |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 86 | #endif |
| 87 | }; |
| 88 | |
| 89 | #define MAXCONTROLLERS 3 |
| 90 | |
| 91 | static int relocated = 0; |
| 92 | |
| 93 | static struct tsec_private *privlist[MAXCONTROLLERS]; |
| 94 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 95 | #ifdef __GNUC__ |
| 96 | static RTXBD rtx __attribute__ ((aligned(8))); |
| 97 | #else |
| 98 | #error "rtx must be 64-bit aligned" |
| 99 | #endif |
| 100 | |
| 101 | static int tsec_send(struct eth_device* dev, volatile void *packet, int length); |
| 102 | static int tsec_recv(struct eth_device* dev); |
| 103 | static int tsec_init(struct eth_device* dev, bd_t * bd); |
| 104 | static void tsec_halt(struct eth_device* dev); |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 105 | static void init_registers(volatile tsec_t *regs); |
| 106 | static void startup_tsec(struct eth_device *dev); |
| 107 | static int init_phy(struct eth_device *dev); |
| 108 | void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); |
| 109 | uint read_phy_reg(struct tsec_private *priv, uint regnum); |
| 110 | struct phy_info * get_phy_info(struct eth_device *dev); |
| 111 | void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); |
| 112 | static void adjust_link(struct eth_device *dev); |
| 113 | static void relocate_cmds(void); |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 114 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 115 | /* Initialize device structure. Returns success if PHY |
| 116 | * initialization succeeded (i.e. if it recognizes the PHY) |
| 117 | */ |
| 118 | int tsec_initialize(bd_t *bis, int index) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 119 | { |
| 120 | struct eth_device* dev; |
| 121 | int i; |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 122 | struct tsec_private *priv; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 123 | |
| 124 | dev = (struct eth_device*) malloc(sizeof *dev); |
| 125 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 126 | if(NULL == dev) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 127 | return 0; |
| 128 | |
| 129 | memset(dev, 0, sizeof *dev); |
| 130 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 131 | priv = (struct tsec_private *) malloc(sizeof(*priv)); |
| 132 | |
| 133 | if(NULL == priv) |
| 134 | return 0; |
| 135 | |
| 136 | privlist[index] = priv; |
| 137 | priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index*TSEC_SIZE); |
| 138 | priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR + |
| 139 | tsec_info[index].phyregidx*TSEC_SIZE); |
| 140 | |
| 141 | priv->phyaddr = tsec_info[index].phyaddr; |
| 142 | priv->gigabit = tsec_info[index].gigabit; |
| 143 | |
| 144 | sprintf(dev->name, "MOTO ENET%d", index); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 145 | dev->iobase = 0; |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 146 | dev->priv = priv; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 147 | dev->init = tsec_init; |
| 148 | dev->halt = tsec_halt; |
| 149 | dev->send = tsec_send; |
| 150 | dev->recv = tsec_recv; |
| 151 | |
| 152 | /* Tell u-boot to get the addr from the env */ |
| 153 | for(i=0;i<6;i++) |
| 154 | dev->enetaddr[i] = 0; |
| 155 | |
| 156 | eth_register(dev); |
| 157 | |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 158 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 159 | /* Reset the MAC */ |
| 160 | priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; |
| 161 | priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 162 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 163 | /* Try to initialize PHY here, and return */ |
| 164 | return init_phy(dev); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 165 | } |
| 166 | |
| 167 | |
| 168 | /* Initializes data structures and registers for the controller, |
wdenk | 9d46ea4 | 2005-03-14 23:56:42 +0000 | [diff] [blame] | 169 | * and brings the interface up. Returns the link status, meaning |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 170 | * that it returns success if the link is up, failure otherwise. |
| 171 | * This allows u-boot to find the first active controller. */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 172 | int tsec_init(struct eth_device* dev, bd_t * bd) |
| 173 | { |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 174 | uint tempval; |
| 175 | char tmpbuf[MAC_ADDR_LEN]; |
| 176 | int i; |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 177 | struct tsec_private *priv = (struct tsec_private *)dev->priv; |
| 178 | volatile tsec_t *regs = priv->regs; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 179 | |
| 180 | /* Make sure the controller is stopped */ |
| 181 | tsec_halt(dev); |
| 182 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 183 | /* Init MACCFG2. Defaults to GMII */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 184 | regs->maccfg2 = MACCFG2_INIT_SETTINGS; |
| 185 | |
| 186 | /* Init ECNTRL */ |
| 187 | regs->ecntrl = ECNTRL_INIT_SETTINGS; |
| 188 | |
| 189 | /* Copy the station address into the address registers. |
| 190 | * Backwards, because little endian MACS are dumb */ |
| 191 | for(i=0;i<MAC_ADDR_LEN;i++) { |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 192 | tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 193 | } |
| 194 | (uint)(regs->macstnaddr1) = *((uint *)(tmpbuf)); |
| 195 | |
| 196 | tempval = *((uint *)(tmpbuf +4)); |
| 197 | |
| 198 | (uint)(regs->macstnaddr2) = tempval; |
| 199 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 200 | /* reset the indices to zero */ |
| 201 | rxIdx = 0; |
| 202 | txIdx = 0; |
| 203 | |
| 204 | /* Clear out (for the most part) the other registers */ |
| 205 | init_registers(regs); |
| 206 | |
| 207 | /* Ready the device for tx/rx */ |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 208 | startup_tsec(dev); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 209 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 210 | /* If there's no link, fail */ |
| 211 | return priv->link; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 212 | |
| 213 | } |
| 214 | |
| 215 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 216 | /* Write value to the device's PHY through the registers |
| 217 | * specified in priv, modifying the register specified in regnum. |
| 218 | * It will wait for the write to be done (or for a timeout to |
| 219 | * expire) before exiting |
| 220 | */ |
| 221 | void write_phy_reg(struct tsec_private *priv, uint regnum, uint value) |
| 222 | { |
| 223 | volatile tsec_t *regbase = priv->phyregs; |
| 224 | uint phyid = priv->phyaddr; |
| 225 | int timeout=1000000; |
| 226 | |
| 227 | regbase->miimadd = (phyid << 8) | regnum; |
| 228 | regbase->miimcon = value; |
| 229 | asm("msync"); |
| 230 | |
| 231 | timeout=1000000; |
| 232 | while((regbase->miimind & MIIMIND_BUSY) && timeout--); |
| 233 | } |
| 234 | |
| 235 | |
| 236 | /* Reads register regnum on the device's PHY through the |
wdenk | 9d46ea4 | 2005-03-14 23:56:42 +0000 | [diff] [blame] | 237 | * registers specified in priv. It lowers and raises the read |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 238 | * command, and waits for the data to become valid (miimind |
| 239 | * notvalid bit cleared), and the bus to cease activity (miimind |
| 240 | * busy bit cleared), and then returns the value |
| 241 | */ |
| 242 | uint read_phy_reg(struct tsec_private *priv, uint regnum) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 243 | { |
| 244 | uint value; |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 245 | volatile tsec_t *regbase = priv->phyregs; |
| 246 | uint phyid = priv->phyaddr; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 247 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 248 | /* Put the address of the phy, and the register |
| 249 | * number into MIIMADD */ |
| 250 | regbase->miimadd = (phyid << 8) | regnum; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 251 | |
| 252 | /* Clear the command register, and wait */ |
| 253 | regbase->miimcom = 0; |
| 254 | asm("msync"); |
| 255 | |
| 256 | /* Initiate a read command, and wait */ |
| 257 | regbase->miimcom = MIIM_READ_COMMAND; |
| 258 | asm("msync"); |
| 259 | |
| 260 | /* Wait for the the indication that the read is done */ |
| 261 | while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))); |
| 262 | |
| 263 | /* Grab the value read from the PHY */ |
| 264 | value = regbase->miimstat; |
| 265 | |
| 266 | return value; |
| 267 | } |
| 268 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 269 | |
| 270 | /* Discover which PHY is attached to the device, and configure it |
| 271 | * properly. If the PHY is not recognized, then return 0 |
| 272 | * (failure). Otherwise, return 1 |
| 273 | */ |
| 274 | static int init_phy(struct eth_device *dev) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 275 | { |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 276 | struct tsec_private *priv = (struct tsec_private *)dev->priv; |
| 277 | struct phy_info *curphy; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 278 | |
| 279 | /* Assign a Physical address to the TBI */ |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 280 | priv->regs->tbipa=TBIPA_VALUE; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 281 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 282 | if(0 == relocated) |
| 283 | relocate_cmds(); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 284 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 285 | /* Get the cmd structure corresponding to the attached |
| 286 | * PHY */ |
| 287 | curphy = get_phy_info(dev); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 288 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 289 | if(NULL == curphy) { |
| 290 | printf("%s: No PHY found\n", dev->name); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 291 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 292 | return 0; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 293 | } |
| 294 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 295 | priv->phyinfo = curphy; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 296 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 297 | phy_run_commands(priv, priv->phyinfo->config); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 298 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 299 | return 1; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 300 | } |
| 301 | |
| 302 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 303 | /* Returns which value to write to the control register. */ |
| 304 | /* For 10/100, the value is slightly different */ |
| 305 | uint mii_cr_init(uint mii_reg, struct tsec_private *priv) |
| 306 | { |
| 307 | if(priv->gigabit) |
| 308 | return MIIM_CONTROL_INIT; |
| 309 | else |
| 310 | return MIIM_CR_INIT; |
| 311 | } |
| 312 | |
| 313 | |
| 314 | /* Parse the status register for link, and then do |
| 315 | * auto-negotiation */ |
| 316 | uint mii_parse_sr(uint mii_reg, struct tsec_private *priv) |
| 317 | { |
| 318 | uint timeout = TSEC_TIMEOUT; |
| 319 | |
| 320 | if(mii_reg & MIIM_STATUS_LINK) |
| 321 | priv->link = 1; |
| 322 | else |
| 323 | priv->link = 0; |
| 324 | |
| 325 | if(priv->link) { |
| 326 | while((!(mii_reg & MIIM_STATUS_AN_DONE)) && timeout--) |
| 327 | mii_reg = read_phy_reg(priv, MIIM_STATUS); |
| 328 | } |
| 329 | |
| 330 | return 0; |
| 331 | } |
| 332 | |
| 333 | |
| 334 | /* Parse the 88E1011's status register for speed and duplex |
| 335 | * information */ |
| 336 | uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv) |
| 337 | { |
| 338 | uint speed; |
| 339 | |
| 340 | if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) |
| 341 | priv->duplexity = 1; |
| 342 | else |
| 343 | priv->duplexity = 0; |
| 344 | |
| 345 | speed = (mii_reg &MIIM_88E1011_PHYSTAT_SPEED); |
| 346 | |
| 347 | switch(speed) { |
| 348 | case MIIM_88E1011_PHYSTAT_GBIT: |
| 349 | priv->speed = 1000; |
| 350 | break; |
| 351 | case MIIM_88E1011_PHYSTAT_100: |
| 352 | priv->speed = 100; |
| 353 | break; |
| 354 | default: |
| 355 | priv->speed = 10; |
| 356 | } |
| 357 | |
| 358 | return 0; |
| 359 | } |
| 360 | |
| 361 | |
| 362 | /* Parse the cis8201's status register for speed and duplex |
| 363 | * information */ |
| 364 | uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv) |
| 365 | { |
| 366 | uint speed; |
| 367 | |
| 368 | if(mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) |
| 369 | priv->duplexity = 1; |
| 370 | else |
| 371 | priv->duplexity = 0; |
| 372 | |
| 373 | speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; |
| 374 | switch(speed) { |
| 375 | case MIIM_CIS8201_AUXCONSTAT_GBIT: |
| 376 | priv->speed = 1000; |
| 377 | break; |
| 378 | case MIIM_CIS8201_AUXCONSTAT_100: |
| 379 | priv->speed = 100; |
| 380 | break; |
| 381 | default: |
| 382 | priv->speed = 10; |
| 383 | break; |
| 384 | } |
| 385 | |
| 386 | return 0; |
| 387 | } |
| 388 | |
| 389 | |
| 390 | /* Parse the DM9161's status register for speed and duplex |
| 391 | * information */ |
| 392 | uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv) |
| 393 | { |
| 394 | if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) |
| 395 | priv->speed = 100; |
| 396 | else |
| 397 | priv->speed = 10; |
| 398 | |
| 399 | if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) |
| 400 | priv->duplexity = 1; |
| 401 | else |
| 402 | priv->duplexity = 0; |
| 403 | |
| 404 | return 0; |
| 405 | } |
| 406 | |
| 407 | |
| 408 | /* Hack to write all 4 PHYs with the LED values */ |
| 409 | uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv) |
| 410 | { |
| 411 | uint phyid; |
| 412 | volatile tsec_t *regbase = priv->phyregs; |
| 413 | int timeout=1000000; |
| 414 | |
| 415 | for(phyid=0;phyid<4;phyid++) { |
| 416 | regbase->miimadd = (phyid << 8) | mii_reg; |
| 417 | regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; |
| 418 | asm("msync"); |
| 419 | |
| 420 | timeout=1000000; |
| 421 | while((regbase->miimind & MIIMIND_BUSY) && timeout--); |
| 422 | } |
| 423 | |
| 424 | return MIIM_CIS8204_SLEDCON_INIT; |
| 425 | } |
| 426 | |
| 427 | |
| 428 | /* Initialized required registers to appropriate values, zeroing |
| 429 | * those we don't care about (unless zero is bad, in which case, |
| 430 | * choose a more appropriate value) */ |
| 431 | static void init_registers(volatile tsec_t *regs) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 432 | { |
| 433 | /* Clear IEVENT */ |
| 434 | regs->ievent = IEVENT_INIT_CLEAR; |
| 435 | |
| 436 | regs->imask = IMASK_INIT_CLEAR; |
| 437 | |
| 438 | regs->hash.iaddr0 = 0; |
| 439 | regs->hash.iaddr1 = 0; |
| 440 | regs->hash.iaddr2 = 0; |
| 441 | regs->hash.iaddr3 = 0; |
| 442 | regs->hash.iaddr4 = 0; |
| 443 | regs->hash.iaddr5 = 0; |
| 444 | regs->hash.iaddr6 = 0; |
| 445 | regs->hash.iaddr7 = 0; |
| 446 | |
| 447 | regs->hash.gaddr0 = 0; |
| 448 | regs->hash.gaddr1 = 0; |
| 449 | regs->hash.gaddr2 = 0; |
| 450 | regs->hash.gaddr3 = 0; |
| 451 | regs->hash.gaddr4 = 0; |
| 452 | regs->hash.gaddr5 = 0; |
| 453 | regs->hash.gaddr6 = 0; |
| 454 | regs->hash.gaddr7 = 0; |
| 455 | |
| 456 | regs->rctrl = 0x00000000; |
| 457 | |
| 458 | /* Init RMON mib registers */ |
| 459 | memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); |
| 460 | |
| 461 | regs->rmon.cam1 = 0xffffffff; |
| 462 | regs->rmon.cam2 = 0xffffffff; |
| 463 | |
| 464 | regs->mrblr = MRBLR_INIT_SETTINGS; |
| 465 | |
| 466 | regs->minflr = MINFLR_INIT_SETTINGS; |
| 467 | |
| 468 | regs->attr = ATTR_INIT_SETTINGS; |
| 469 | regs->attreli = ATTRELI_INIT_SETTINGS; |
| 470 | |
| 471 | } |
| 472 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 473 | |
| 474 | /* Configure maccfg2 based on negotiated speed and duplex |
| 475 | * reported by PHY handling code */ |
| 476 | static void adjust_link(struct eth_device *dev) |
| 477 | { |
| 478 | struct tsec_private *priv = (struct tsec_private *)dev->priv; |
| 479 | volatile tsec_t *regs = priv->regs; |
| 480 | |
| 481 | if(priv->link) { |
| 482 | if(priv->duplexity != 0) |
| 483 | regs->maccfg2 |= MACCFG2_FULL_DUPLEX; |
| 484 | else |
| 485 | regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); |
| 486 | |
| 487 | switch(priv->speed) { |
| 488 | case 1000: |
| 489 | regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) |
| 490 | | MACCFG2_GMII); |
| 491 | break; |
| 492 | case 100: |
| 493 | case 10: |
| 494 | regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) |
| 495 | | MACCFG2_MII); |
| 496 | break; |
| 497 | default: |
| 498 | printf("%s: Speed was bad\n", dev->name); |
| 499 | break; |
| 500 | } |
| 501 | |
| 502 | printf("Speed: %d, %s duplex\n", priv->speed, |
| 503 | (priv->duplexity) ? "full" : "half"); |
| 504 | |
| 505 | } else { |
| 506 | printf("%s: No link.\n", dev->name); |
| 507 | } |
| 508 | } |
| 509 | |
| 510 | |
| 511 | /* Set up the buffers and their descriptors, and bring up the |
| 512 | * interface */ |
| 513 | static void startup_tsec(struct eth_device *dev) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 514 | { |
| 515 | int i; |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 516 | struct tsec_private *priv = (struct tsec_private *)dev->priv; |
| 517 | volatile tsec_t *regs = priv->regs; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 518 | |
| 519 | /* Point to the buffer descriptors */ |
| 520 | regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); |
| 521 | regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); |
| 522 | |
| 523 | /* Initialize the Rx Buffer descriptors */ |
| 524 | for (i = 0; i < PKTBUFSRX; i++) { |
| 525 | rtx.rxbd[i].status = RXBD_EMPTY; |
| 526 | rtx.rxbd[i].length = 0; |
| 527 | rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i]; |
| 528 | } |
| 529 | rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP; |
| 530 | |
| 531 | /* Initialize the TX Buffer Descriptors */ |
| 532 | for(i=0; i<TX_BUF_CNT; i++) { |
| 533 | rtx.txbd[i].status = 0; |
| 534 | rtx.txbd[i].length = 0; |
| 535 | rtx.txbd[i].bufPtr = 0; |
| 536 | } |
| 537 | rtx.txbd[TX_BUF_CNT -1].status |= TXBD_WRAP; |
| 538 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 539 | /* Start up the PHY */ |
| 540 | phy_run_commands(priv, priv->phyinfo->startup); |
| 541 | adjust_link(dev); |
| 542 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 543 | /* Enable Transmit and Receive */ |
| 544 | regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); |
| 545 | |
| 546 | /* Tell the DMA it is clear to go */ |
| 547 | regs->dmactrl |= DMACTRL_INIT_SETTINGS; |
| 548 | regs->tstat = TSTAT_CLEAR_THALT; |
| 549 | regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); |
| 550 | } |
| 551 | |
wdenk | 9d46ea4 | 2005-03-14 23:56:42 +0000 | [diff] [blame] | 552 | /* This returns the status bits of the device. The return value |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 553 | * is never checked, and this is what the 8260 driver did, so we |
wdenk | 9d46ea4 | 2005-03-14 23:56:42 +0000 | [diff] [blame] | 554 | * do the same. Presumably, this would be zero if there were no |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 555 | * errors */ |
| 556 | static int tsec_send(struct eth_device* dev, volatile void *packet, int length) |
| 557 | { |
| 558 | int i; |
| 559 | int result = 0; |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 560 | struct tsec_private *priv = (struct tsec_private *)dev->priv; |
| 561 | volatile tsec_t *regs = priv->regs; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 562 | |
| 563 | /* Find an empty buffer descriptor */ |
| 564 | for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) { |
| 565 | if (i >= TOUT_LOOP) { |
wdenk | 8b07a11 | 2004-07-10 21:45:47 +0000 | [diff] [blame] | 566 | debug ("%s: tsec: tx buffers full\n", dev->name); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 567 | return result; |
| 568 | } |
| 569 | } |
| 570 | |
| 571 | rtx.txbd[txIdx].bufPtr = (uint)packet; |
| 572 | rtx.txbd[txIdx].length = length; |
| 573 | rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); |
| 574 | |
| 575 | /* Tell the DMA to go */ |
| 576 | regs->tstat = TSTAT_CLEAR_THALT; |
| 577 | |
| 578 | /* Wait for buffer to be transmitted */ |
| 579 | for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) { |
| 580 | if (i >= TOUT_LOOP) { |
wdenk | 8b07a11 | 2004-07-10 21:45:47 +0000 | [diff] [blame] | 581 | debug ("%s: tsec: tx error\n", dev->name); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 582 | return result; |
| 583 | } |
| 584 | } |
| 585 | |
| 586 | txIdx = (txIdx + 1) % TX_BUF_CNT; |
| 587 | result = rtx.txbd[txIdx].status & TXBD_STATS; |
| 588 | |
| 589 | return result; |
| 590 | } |
| 591 | |
| 592 | static int tsec_recv(struct eth_device* dev) |
| 593 | { |
| 594 | int length; |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 595 | struct tsec_private *priv = (struct tsec_private *)dev->priv; |
| 596 | volatile tsec_t *regs = priv->regs; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 597 | |
| 598 | while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { |
| 599 | |
| 600 | length = rtx.rxbd[rxIdx].length; |
| 601 | |
| 602 | /* Send the packet up if there were no errors */ |
| 603 | if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { |
| 604 | NetReceive(NetRxPackets[rxIdx], length - 4); |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 605 | } else { |
| 606 | printf("Got error %x\n", |
| 607 | (rtx.rxbd[rxIdx].status & RXBD_STATS)); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 608 | } |
| 609 | |
| 610 | rtx.rxbd[rxIdx].length = 0; |
| 611 | |
| 612 | /* Set the wrap bit if this is the last element in the list */ |
| 613 | rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); |
| 614 | |
| 615 | rxIdx = (rxIdx + 1) % PKTBUFSRX; |
| 616 | } |
| 617 | |
| 618 | if(regs->ievent&IEVENT_BSY) { |
| 619 | regs->ievent = IEVENT_BSY; |
| 620 | regs->rstat = RSTAT_CLEAR_RHALT; |
| 621 | } |
| 622 | |
| 623 | return -1; |
| 624 | |
| 625 | } |
| 626 | |
| 627 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 628 | /* Stop the interface */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 629 | static void tsec_halt(struct eth_device* dev) |
| 630 | { |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 631 | struct tsec_private *priv = (struct tsec_private *)dev->priv; |
| 632 | volatile tsec_t *regs = priv->regs; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 633 | |
| 634 | regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); |
| 635 | regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); |
| 636 | |
| 637 | while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))); |
| 638 | |
| 639 | regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); |
| 640 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 641 | /* Shut down the PHY, as needed */ |
| 642 | phy_run_commands(priv, priv->phyinfo->shutdown); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 643 | } |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 644 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 645 | |
| 646 | struct phy_info phy_info_M88E1011S = { |
| 647 | 0x01410c6, |
| 648 | "Marvell 88E1011S", |
| 649 | 4, |
| 650 | (struct phy_cmd[]) { /* config */ |
| 651 | /* Reset and configure the PHY */ |
| 652 | {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, |
| 653 | {0x1d, 0x1f, NULL}, |
| 654 | {0x1e, 0x200c, NULL}, |
| 655 | {0x1d, 0x5, NULL}, |
| 656 | {0x1e, 0x0, NULL}, |
| 657 | {0x1e, 0x100, NULL}, |
| 658 | {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, |
| 659 | {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, |
| 660 | {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, |
| 661 | {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, |
| 662 | {miim_end,} |
| 663 | }, |
| 664 | (struct phy_cmd[]) { /* startup */ |
| 665 | /* Status is read once to clear old link state */ |
| 666 | {MIIM_STATUS, miim_read, NULL}, |
| 667 | /* Auto-negotiate */ |
| 668 | {MIIM_STATUS, miim_read, &mii_parse_sr}, |
| 669 | /* Read the status */ |
| 670 | {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, |
| 671 | {miim_end,} |
| 672 | }, |
| 673 | (struct phy_cmd[]) { /* shutdown */ |
| 674 | {miim_end,} |
| 675 | }, |
| 676 | }; |
| 677 | |
wdenk | 9d46ea4 | 2005-03-14 23:56:42 +0000 | [diff] [blame] | 678 | struct phy_info phy_info_M88E1111S = { |
| 679 | 0x01410cc, |
| 680 | "Marvell 88E1111S", |
| 681 | 4, |
| 682 | (struct phy_cmd[]) { /* config */ |
| 683 | /* Reset and configure the PHY */ |
| 684 | {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, |
| 685 | {0x1d, 0x1f, NULL}, |
| 686 | {0x1e, 0x200c, NULL}, |
| 687 | {0x1d, 0x5, NULL}, |
| 688 | {0x1e, 0x0, NULL}, |
| 689 | {0x1e, 0x100, NULL}, |
| 690 | {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, |
| 691 | {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, |
| 692 | {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, |
| 693 | {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, |
| 694 | {miim_end,} |
| 695 | }, |
| 696 | (struct phy_cmd[]) { /* startup */ |
| 697 | /* Status is read once to clear old link state */ |
| 698 | {MIIM_STATUS, miim_read, NULL}, |
| 699 | /* Auto-negotiate */ |
| 700 | {MIIM_STATUS, miim_read, &mii_parse_sr}, |
| 701 | /* Read the status */ |
| 702 | {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, |
| 703 | {miim_end,} |
| 704 | }, |
| 705 | (struct phy_cmd[]) { /* shutdown */ |
| 706 | {miim_end,} |
| 707 | }, |
| 708 | }; |
| 709 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 710 | struct phy_info phy_info_cis8204 = { |
| 711 | 0x3f11, |
| 712 | "Cicada Cis8204", |
| 713 | 6, |
| 714 | (struct phy_cmd[]) { /* config */ |
| 715 | /* Override PHY config settings */ |
| 716 | {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, |
| 717 | /* Configure some basic stuff */ |
| 718 | {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, |
| 719 | {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled}, |
| 720 | {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, NULL}, |
| 721 | {miim_end,} |
| 722 | }, |
| 723 | (struct phy_cmd[]) { /* startup */ |
| 724 | /* Read the Status (2x to make sure link is right) */ |
| 725 | {MIIM_STATUS, miim_read, NULL}, |
| 726 | /* Auto-negotiate */ |
| 727 | {MIIM_STATUS, miim_read, &mii_parse_sr}, |
| 728 | /* Read the status */ |
| 729 | {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, |
| 730 | {miim_end,} |
| 731 | }, |
| 732 | (struct phy_cmd[]) { /* shutdown */ |
| 733 | {miim_end,} |
| 734 | }, |
| 735 | }; |
| 736 | |
| 737 | /* Cicada 8201 */ |
| 738 | struct phy_info phy_info_cis8201 = { |
| 739 | 0xfc41, |
| 740 | "CIS8201", |
| 741 | 4, |
| 742 | (struct phy_cmd[]) { /* config */ |
| 743 | /* Override PHY config settings */ |
| 744 | {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, |
| 745 | /* Set up the interface mode */ |
| 746 | {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, |
| 747 | /* Configure some basic stuff */ |
| 748 | {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, |
| 749 | {miim_end,} |
| 750 | }, |
| 751 | (struct phy_cmd[]) { /* startup */ |
| 752 | /* Read the Status (2x to make sure link is right) */ |
| 753 | {MIIM_STATUS, miim_read, NULL}, |
| 754 | /* Auto-negotiate */ |
| 755 | {MIIM_STATUS, miim_read, &mii_parse_sr}, |
| 756 | /* Read the status */ |
| 757 | {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, |
| 758 | {miim_end,} |
| 759 | }, |
| 760 | (struct phy_cmd[]) { /* shutdown */ |
| 761 | {miim_end,} |
| 762 | }, |
| 763 | }; |
| 764 | |
| 765 | |
| 766 | struct phy_info phy_info_dm9161 = { |
| 767 | 0x0181b88, |
| 768 | "Davicom DM9161E", |
| 769 | 4, |
| 770 | (struct phy_cmd[]) { /* config */ |
| 771 | {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, |
| 772 | /* Do not bypass the scrambler/descrambler */ |
| 773 | {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, |
| 774 | /* Clear 10BTCSR to default */ |
| 775 | {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL}, |
| 776 | /* Configure some basic stuff */ |
| 777 | {MIIM_CONTROL, MIIM_CR_INIT, NULL}, |
| 778 | /* Restart Auto Negotiation */ |
| 779 | {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, |
| 780 | {miim_end,} |
| 781 | }, |
| 782 | (struct phy_cmd[]) { /* startup */ |
| 783 | /* Status is read once to clear old link state */ |
| 784 | {MIIM_STATUS, miim_read, NULL}, |
| 785 | /* Auto-negotiate */ |
| 786 | {MIIM_STATUS, miim_read, &mii_parse_sr}, |
| 787 | /* Read the status */ |
| 788 | {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr}, |
| 789 | {miim_end,} |
| 790 | }, |
| 791 | (struct phy_cmd[]) { /* shutdown */ |
| 792 | {miim_end,} |
| 793 | }, |
| 794 | }; |
| 795 | |
wdenk | 9d46ea4 | 2005-03-14 23:56:42 +0000 | [diff] [blame] | 796 | static struct phy_info phy_info_lxt971 = { |
| 797 | 0x0001378e, |
| 798 | "LXT971", |
| 799 | 4, |
| 800 | (struct phy_cmd []) { /* config */ |
| 801 | { MIIM_CONTROL, MIIM_CONTROL_INIT, mii_cr_init }, /* autonegotiate */ |
| 802 | { miim_end, } |
| 803 | }, |
| 804 | (struct phy_cmd []) { /* startup - enable interrupts */ |
| 805 | /* { 0x12, 0x00f2, NULL }, */ |
| 806 | { 0x14, 0xd422, NULL }, /* LED config */ |
| 807 | { MIIM_STATUS, miim_read, NULL }, |
| 808 | { MIIM_STATUS, miim_read, mii_parse_sr }, |
| 809 | { miim_end, } |
| 810 | }, |
| 811 | (struct phy_cmd []) { /* shutdown - disable interrupts */ |
| 812 | { miim_end, } |
| 813 | }, |
| 814 | }; |
| 815 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 816 | struct phy_info *phy_info[] = { |
| 817 | #if 0 |
| 818 | &phy_info_cis8201, |
| 819 | #endif |
| 820 | &phy_info_cis8204, |
| 821 | &phy_info_M88E1011S, |
wdenk | 9d46ea4 | 2005-03-14 23:56:42 +0000 | [diff] [blame] | 822 | &phy_info_M88E1111S, |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 823 | &phy_info_dm9161, |
wdenk | 9d46ea4 | 2005-03-14 23:56:42 +0000 | [diff] [blame] | 824 | &phy_info_lxt971, |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 825 | NULL |
| 826 | }; |
| 827 | |
| 828 | |
| 829 | /* Grab the identifier of the device's PHY, and search through |
wdenk | 9d46ea4 | 2005-03-14 23:56:42 +0000 | [diff] [blame] | 830 | * all of the known PHYs to see if one matches. If so, return |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 831 | * it, if not, return NULL */ |
| 832 | struct phy_info * get_phy_info(struct eth_device *dev) |
| 833 | { |
| 834 | struct tsec_private *priv = (struct tsec_private *)dev->priv; |
| 835 | uint phy_reg, phy_ID; |
| 836 | int i; |
| 837 | struct phy_info *theInfo = NULL; |
| 838 | |
| 839 | /* Grab the bits from PHYIR1, and put them in the upper half */ |
| 840 | phy_reg = read_phy_reg(priv, MIIM_PHYIR1); |
| 841 | phy_ID = (phy_reg & 0xffff) << 16; |
| 842 | |
| 843 | /* Grab the bits from PHYIR2, and put them in the lower half */ |
| 844 | phy_reg = read_phy_reg(priv, MIIM_PHYIR2); |
| 845 | phy_ID |= (phy_reg & 0xffff); |
| 846 | |
| 847 | /* loop through all the known PHY types, and find one that */ |
| 848 | /* matches the ID we read from the PHY. */ |
| 849 | for(i=0; phy_info[i]; i++) { |
| 850 | if(phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) |
| 851 | theInfo = phy_info[i]; |
| 852 | } |
| 853 | |
| 854 | if(theInfo == NULL) |
| 855 | { |
| 856 | printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID); |
| 857 | return NULL; |
| 858 | } else { |
| 859 | printf("%s: PHY is %s (%x)\n", dev->name, theInfo->name, |
| 860 | phy_ID); |
| 861 | } |
| 862 | |
| 863 | return theInfo; |
| 864 | } |
| 865 | |
| 866 | |
| 867 | /* Execute the given series of commands on the given device's |
| 868 | * PHY, running functions as necessary*/ |
| 869 | void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) |
| 870 | { |
| 871 | int i; |
| 872 | uint result; |
| 873 | volatile tsec_t *phyregs = priv->phyregs; |
| 874 | |
| 875 | phyregs->miimcfg = MIIMCFG_RESET; |
| 876 | |
| 877 | phyregs->miimcfg = MIIMCFG_INIT_VALUE; |
| 878 | |
| 879 | while(phyregs->miimind & MIIMIND_BUSY); |
| 880 | |
| 881 | for(i=0;cmd->mii_reg != miim_end;i++) { |
| 882 | if(cmd->mii_data == miim_read) { |
| 883 | result = read_phy_reg(priv, cmd->mii_reg); |
| 884 | |
| 885 | if(cmd->funct != NULL) |
| 886 | (*(cmd->funct))(result, priv); |
| 887 | |
| 888 | } else { |
| 889 | if(cmd->funct != NULL) |
| 890 | result = (*(cmd->funct))(cmd->mii_reg, priv); |
| 891 | else |
| 892 | result = cmd->mii_data; |
| 893 | |
| 894 | write_phy_reg(priv, cmd->mii_reg, result); |
| 895 | |
| 896 | } |
| 897 | cmd++; |
| 898 | } |
| 899 | } |
| 900 | |
| 901 | |
| 902 | /* Relocate the function pointers in the phy cmd lists */ |
| 903 | static void relocate_cmds(void) |
| 904 | { |
| 905 | struct phy_cmd **cmdlistptr; |
| 906 | struct phy_cmd *cmd; |
| 907 | int i,j,k; |
| 908 | DECLARE_GLOBAL_DATA_PTR; |
| 909 | |
| 910 | for(i=0; phy_info[i]; i++) { |
| 911 | /* First thing's first: relocate the pointers to the |
| 912 | * PHY command structures (the structs were done) */ |
| 913 | phy_info[i] = (struct phy_info *) ((uint)phy_info[i] |
| 914 | + gd->reloc_off); |
| 915 | phy_info[i]->name += gd->reloc_off; |
| 916 | phy_info[i]->config = |
| 917 | (struct phy_cmd *)((uint)phy_info[i]->config |
| 918 | + gd->reloc_off); |
| 919 | phy_info[i]->startup = |
| 920 | (struct phy_cmd *)((uint)phy_info[i]->startup |
| 921 | + gd->reloc_off); |
| 922 | phy_info[i]->shutdown = |
| 923 | (struct phy_cmd *)((uint)phy_info[i]->shutdown |
| 924 | + gd->reloc_off); |
| 925 | |
| 926 | cmdlistptr = &phy_info[i]->config; |
| 927 | j=0; |
| 928 | for(;cmdlistptr <= &phy_info[i]->shutdown;cmdlistptr++) { |
| 929 | k=0; |
| 930 | for(cmd=*cmdlistptr;cmd->mii_reg != miim_end;cmd++) { |
| 931 | /* Only relocate non-NULL pointers */ |
| 932 | if(cmd->funct) |
| 933 | cmd->funct += gd->reloc_off; |
| 934 | |
| 935 | k++; |
| 936 | } |
| 937 | j++; |
| 938 | } |
| 939 | } |
| 940 | |
| 941 | relocated = 1; |
| 942 | } |
| 943 | |
| 944 | |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 945 | #ifndef CONFIG_BITBANGMII |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 946 | |
| 947 | struct tsec_private * get_priv_for_phy(unsigned char phyaddr) |
| 948 | { |
| 949 | int i; |
| 950 | |
| 951 | for(i=0;i<MAXCONTROLLERS;i++) { |
| 952 | if(privlist[i]->phyaddr == phyaddr) |
| 953 | return privlist[i]; |
| 954 | } |
| 955 | |
| 956 | return NULL; |
| 957 | } |
| 958 | |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 959 | /* |
| 960 | * Read a MII PHY register. |
| 961 | * |
| 962 | * Returns: |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 963 | * 0 on success |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 964 | */ |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 965 | int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value) |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 966 | { |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 967 | unsigned short ret; |
| 968 | struct tsec_private *priv = get_priv_for_phy(addr); |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 969 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 970 | if(NULL == priv) { |
| 971 | printf("Can't read PHY at address %d\n", addr); |
| 972 | return -1; |
| 973 | } |
| 974 | |
| 975 | ret = (unsigned short)read_phy_reg(priv, reg); |
| 976 | *value = ret; |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 977 | |
| 978 | return 0; |
| 979 | } |
| 980 | |
| 981 | /* |
| 982 | * Write a MII PHY register. |
| 983 | * |
| 984 | * Returns: |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 985 | * 0 on success |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 986 | */ |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 987 | int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value) |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 988 | { |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 989 | struct tsec_private *priv = get_priv_for_phy(addr); |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 990 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 991 | if(NULL == priv) { |
| 992 | printf("Can't write PHY at address %d\n", addr); |
| 993 | return -1; |
| 994 | } |
| 995 | |
| 996 | write_phy_reg(priv, reg, value); |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 997 | |
| 998 | return 0; |
| 999 | } |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 1000 | |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 1001 | #endif /* CONFIG_BITBANGMII */ |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 1002 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1003 | #endif /* CONFIG_TSEC_ENET */ |