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Stefan Roese8e1a3fe2008-03-11 16:51:17 +01001/*
2 * (C) Copyright 2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <ppc_asm.tmpl>
25#include <config.h>
26#include <asm-ppc/mmu.h>
27
28/**************************************************************************
29 * TLB TABLE
30 *
31 * This table is used by the cpu boot code to setup the initial tlb
32 * entries. Rather than make broad assumptions in the cpu source tree,
33 * this table lets each board set things up however they like.
34 *
35 * Pointer to the table is returned in r1
36 *
37 *************************************************************************/
38 .section .bootpg,"ax"
39 .globl tlbtab
40
41tlbtab:
42 tlbtab_start
43
44 /*
45 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
46 * use the speed up boot process. It is patched after relocation to
47 * enable SA_I
48 */
Stefan Roese71665eb2008-03-03 17:27:02 +010049#ifndef CONFIG_NAND_SPL
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010050 tlbentry(CFG_BOOT_BASE_ADDR, SZ_16M, CFG_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
Stefan Roese71665eb2008-03-03 17:27:02 +010051#else
52 tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
53 tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
Stefan Roese499e7832008-04-08 10:33:29 +020054 tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
Stefan Roese71665eb2008-03-03 17:27:02 +010055#endif
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010056
57 /*
58 * TLB entries for SDRAM are not needed on this platform.
59 * They are dynamically generated in the SPD DDR(2) detection
60 * routine.
61 */
62
63#ifdef CFG_INIT_RAM_DCACHE
64 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
65 tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
66#endif
67
68 tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
69 tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
70 tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
71
72 tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
73 tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
74 tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
75 tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
76
77 /* PCIe UTL register */
78 tlbentry(CFG_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
79
80 /* TLB-entry for NAND */
81 tlbentry(CFG_NAND_ADDR, SZ_16M, CFG_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
82
83 /* TLB-entry for CPLD */
84 tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
85
86 /* TLB-entry for OCM */
Stefan Roese71665eb2008-03-03 17:27:02 +010087 tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010088
89 /* TLB-entry for Local Configuration registers => peripherals */
90 tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
91
Stefan Roese41712b42008-03-05 12:31:53 +010092 /* AHB: Internal USB Peripherals (USB, SATA) */
93 tlbentry(CFG_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
94
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010095 tlbtab_end
96
97#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
98 /*
99 * For NAND booting the first TLB has to be reconfigured to full size
100 * and with caching disabled after running from RAM!
101 */
102#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
103#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1)
104#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
105
106 .globl reconfig_tlb0
107reconfig_tlb0:
108 sync
109 isync
110 addi r4,r0,0x0000 /* TLB entry #0 */
111 lis r5,TLB00@h
112 ori r5,r5,TLB00@l
113 tlbwe r5,r4,0x0000 /* Save it out */
114 lis r5,TLB01@h
115 ori r5,r5,TLB01@l
116 tlbwe r5,r4,0x0001 /* Save it out */
117 lis r5,TLB02@h
118 ori r5,r5,TLB02@l
119 tlbwe r5,r4,0x0002 /* Save it out */
120 sync
121 isync
122 blr
123#endif