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wdenk7ebf7442002-11-02 23:17:16 +00001/*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
4 * (C) Copyright 2001 ELTEC Elektronik AG
5 * Frank Gottschling <fgottschling@eltec.de>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <command.h>
28#include <mpc106.h>
29#include <mk48t59.h>
30#include <74xx_7xx.h>
31#include <ns87308.h>
32#include <video_fb.h>
Ben Warren8ca0b3f2008-08-31 10:45:44 -070033#include <netdev.h>
wdenk7ebf7442002-11-02 23:17:16 +000034
Wolfgang Denkd87080b2006-03-31 18:32:53 +020035DECLARE_GLOBAL_DATA_PTR;
36
wdenk7ebf7442002-11-02 23:17:16 +000037/*---------------------------------------------------------------------------*/
38/*
39 * Get Bus clock frequency
40 */
41ulong bab7xx_get_bus_freq (void)
42{
wdenkbf9e3b32004-02-12 00:47:09 +000043 /*
44 * The GPIO Port 1 on BAB7xx reflects the bus speed.
45 */
46 volatile struct GPIO *gpio =
47 (struct GPIO *) (CFG_ISA_IO + CFG_NS87308_GPIO_BASE);
wdenk7ebf7442002-11-02 23:17:16 +000048
wdenkbf9e3b32004-02-12 00:47:09 +000049 unsigned char data = gpio->dta1;
wdenk7ebf7442002-11-02 23:17:16 +000050
wdenkbf9e3b32004-02-12 00:47:09 +000051 if (data & 0x02)
52 return 66666666;
wdenk7ebf7442002-11-02 23:17:16 +000053
wdenkbf9e3b32004-02-12 00:47:09 +000054 return 83333333;
wdenk7ebf7442002-11-02 23:17:16 +000055}
56
57/*---------------------------------------------------------------------------*/
58
59/*
60 * Measure CPU clock speed (core clock GCLK1) (Approx. GCLK frequency in Hz)
61 */
62ulong bab7xx_get_gclk_freq (void)
63{
wdenkbf9e3b32004-02-12 00:47:09 +000064 static const int pllratio_to_factor[] = {
65 00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35,
66 00,
67 };
wdenk7ebf7442002-11-02 23:17:16 +000068
wdenkbf9e3b32004-02-12 00:47:09 +000069 return pllratio_to_factor[get_hid1 () >> 28] *
70 (bab7xx_get_bus_freq () / 10);
wdenk7ebf7442002-11-02 23:17:16 +000071}
72
73/*----------------------------------------------------------------------------*/
74
75int checkcpu (void)
76{
wdenkbf9e3b32004-02-12 00:47:09 +000077 uint pvr = get_pvr ();
wdenk7ebf7442002-11-02 23:17:16 +000078
wdenkbf9e3b32004-02-12 00:47:09 +000079 printf ("MPC7xx V%d.%d", (pvr >> 8) & 0xFF, pvr & 0xFF);
80 printf (" at %ld / %ld MHz\n", bab7xx_get_gclk_freq () / 1000000,
81 bab7xx_get_bus_freq () / 1000000);
wdenk7ebf7442002-11-02 23:17:16 +000082
wdenkbf9e3b32004-02-12 00:47:09 +000083 return (0);
wdenk7ebf7442002-11-02 23:17:16 +000084}
85
86/* ------------------------------------------------------------------------- */
87
88int checkboard (void)
89{
90#ifdef CFG_ADDRESS_MAP_A
wdenkbf9e3b32004-02-12 00:47:09 +000091 puts ("Board: ELTEC BAB7xx PReP\n");
wdenk7ebf7442002-11-02 23:17:16 +000092#else
wdenkbf9e3b32004-02-12 00:47:09 +000093 puts ("Board: ELTEC BAB7xx CHRP\n");
wdenk7ebf7442002-11-02 23:17:16 +000094#endif
wdenkbf9e3b32004-02-12 00:47:09 +000095 return (0);
wdenk7ebf7442002-11-02 23:17:16 +000096}
97
98/* ------------------------------------------------------------------------- */
99
100int checkflash (void)
101{
wdenkbf9e3b32004-02-12 00:47:09 +0000102 /* TODO: XXX XXX XXX */
103 printf ("2 MB ## Test not implemented yet ##\n");
104 return (0);
wdenk7ebf7442002-11-02 23:17:16 +0000105}
106
107/* ------------------------------------------------------------------------- */
108
109
110static unsigned int mpc106_read_cfg_dword (unsigned int reg)
111{
wdenkbf9e3b32004-02-12 00:47:09 +0000112 unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
wdenk7ebf7442002-11-02 23:17:16 +0000113
wdenkbf9e3b32004-02-12 00:47:09 +0000114 out32r (MPC106_REG_ADDR, reg_addr);
wdenk7ebf7442002-11-02 23:17:16 +0000115
wdenkbf9e3b32004-02-12 00:47:09 +0000116 return (in32r (MPC106_REG_DATA | (reg & 0x3)));
wdenk7ebf7442002-11-02 23:17:16 +0000117}
118
119/* ------------------------------------------------------------------------- */
120
121long int dram_size (int board_type)
122{
wdenkbf9e3b32004-02-12 00:47:09 +0000123 /* No actual initialisation to do - done when setting up
124 * PICRs MCCRs ME/SARs etc in ram_init.S.
125 */
wdenk7ebf7442002-11-02 23:17:16 +0000126
wdenkbf9e3b32004-02-12 00:47:09 +0000127 register unsigned long i, msar1, mear1, memSize;
wdenk7ebf7442002-11-02 23:17:16 +0000128
129#if defined(CFG_MEMTEST)
wdenkbf9e3b32004-02-12 00:47:09 +0000130 register unsigned long reg;
wdenk7ebf7442002-11-02 23:17:16 +0000131
wdenkbf9e3b32004-02-12 00:47:09 +0000132 printf ("Testing DRAM\n");
wdenk7ebf7442002-11-02 23:17:16 +0000133
wdenkbf9e3b32004-02-12 00:47:09 +0000134 /* write each mem addr with it's address */
135 for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4)
136 *reg = reg;
wdenk7ebf7442002-11-02 23:17:16 +0000137
wdenkbf9e3b32004-02-12 00:47:09 +0000138 for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) {
139 if (*reg != reg)
140 return -1;
141 }
wdenk7ebf7442002-11-02 23:17:16 +0000142#endif
143
wdenkbf9e3b32004-02-12 00:47:09 +0000144 /*
145 * Since MPC106 memory controller chip has already been set to
146 * control all memory, just read and interpret its memory boundery register.
147 */
148 memSize = 0;
149 msar1 = mpc106_read_cfg_dword (MPC106_MSAR1);
150 mear1 = mpc106_read_cfg_dword (MPC106_MEAR1);
151 i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf;
wdenk7ebf7442002-11-02 23:17:16 +0000152
wdenkbf9e3b32004-02-12 00:47:09 +0000153 do {
154 if (i & 0x01) /* is bank enabled ? */
155 memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
156 msar1 >>= 8;
157 mear1 >>= 8;
158 i >>= 1;
159 } while (i);
wdenk7ebf7442002-11-02 23:17:16 +0000160
wdenkbf9e3b32004-02-12 00:47:09 +0000161 return (memSize * 0x100000);
wdenk7ebf7442002-11-02 23:17:16 +0000162}
163
164/* ------------------------------------------------------------------------- */
165
Becky Bruce9973e3c2008-06-09 16:03:40 -0500166phys_size_t initdram (int board_type)
wdenk7ebf7442002-11-02 23:17:16 +0000167{
wdenkbf9e3b32004-02-12 00:47:09 +0000168 return dram_size (board_type);
wdenk7ebf7442002-11-02 23:17:16 +0000169}
170
171/* ------------------------------------------------------------------------- */
172
173void after_reloc (ulong dest_addr)
174{
wdenkbf9e3b32004-02-12 00:47:09 +0000175 /*
176 * Jump to the main U-Boot board init code
177 */
178 board_init_r ((gd_t *) gd, dest_addr);
wdenk7ebf7442002-11-02 23:17:16 +0000179}
180
181/* ------------------------------------------------------------------------- */
182
183/*
184 * do_reset is done here because in this case it is board specific, since the
185 * 7xx CPUs can only be reset by external HW (the RTC in this case).
186 */
wdenkbf9e3b32004-02-12 00:47:09 +0000187void do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
wdenk7ebf7442002-11-02 23:17:16 +0000188{
189#if defined(CONFIG_RTC_MK48T59)
wdenkbf9e3b32004-02-12 00:47:09 +0000190 /* trigger watchdog immediately */
191 rtc_set_watchdog (1, RTC_WD_RB_16TH);
wdenk7ebf7442002-11-02 23:17:16 +0000192#else
wdenkbf9e3b32004-02-12 00:47:09 +0000193#error "You must define the macro CONFIG_RTC_MK48T59."
wdenk7ebf7442002-11-02 23:17:16 +0000194#endif
195}
196
197/* ------------------------------------------------------------------------- */
198
199#if defined(CONFIG_WATCHDOG)
200/*
201 * Since the 7xx CPUs don't have an internal watchdog, this function is
202 * board specific. We use the RTC here.
203 */
wdenkbf9e3b32004-02-12 00:47:09 +0000204void watchdog_reset (void)
wdenk7ebf7442002-11-02 23:17:16 +0000205{
206#if defined(CONFIG_RTC_MK48T59)
wdenkbf9e3b32004-02-12 00:47:09 +0000207 /* we use a 32 sec watchdog timer */
208 rtc_set_watchdog (8, RTC_WD_RB_4);
wdenk7ebf7442002-11-02 23:17:16 +0000209#else
wdenkbf9e3b32004-02-12 00:47:09 +0000210#error "You must define the macro CONFIG_RTC_MK48T59."
wdenk7ebf7442002-11-02 23:17:16 +0000211#endif
212}
wdenkbf9e3b32004-02-12 00:47:09 +0000213#endif /* CONFIG_WATCHDOG */
wdenk7ebf7442002-11-02 23:17:16 +0000214
215/* ------------------------------------------------------------------------- */
216
217#ifdef CONFIG_CONSOLE_EXTRA_INFO
218extern GraphicDevice smi;
219
220void video_get_info_str (int line_number, char *info)
221{
wdenkbf9e3b32004-02-12 00:47:09 +0000222 /* init video info strings for graphic console */
223 switch (line_number) {
224 case 1:
225 sprintf (info, " MPC7xx V%d.%d at %ld / %ld MHz",
226 (get_pvr () >> 8) & 0xFF,
227 get_pvr () & 0xFF,
228 bab7xx_get_gclk_freq () / 1000000,
229 bab7xx_get_bus_freq () / 1000000);
230 return;
231 case 2:
232 sprintf (info,
233 " ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH",
234 dram_size (0) / 0x100000, flash_init () / 0x100000);
235 return;
236 case 3:
237 sprintf (info, " %s", smi.modeIdent);
238 return;
239 }
wdenk7ebf7442002-11-02 23:17:16 +0000240
wdenkbf9e3b32004-02-12 00:47:09 +0000241 /* no more info lines */
242 *info = 0;
243 return;
wdenk7ebf7442002-11-02 23:17:16 +0000244}
245#endif
246
247/*---------------------------------------------------------------------------*/
Ben Warren8ca0b3f2008-08-31 10:45:44 -0700248
249int board_eth_init(bd_t *bis)
250{
251 return pci_eth_init(bis);
252}