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Kumar Gala3b558e22008-01-17 02:02:10 -06001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/mmu.h>
28
29struct fsl_e_tlb_entry tlb_table[] = {
30 /* TLB 0 - for temp stack in cache */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020031 SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
32 MAS3_SX | MAS3_SW | MAS3_SR, 0,
33 0, 0, BOOKE_PAGESZ_4K, 0),
34 SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 4 * 1024,
35 CFG_INIT_RAM_ADDR + 4 * 1024,
36 MAS3_SX | MAS3_SW | MAS3_SR, 0,
37 0, 0, BOOKE_PAGESZ_4K, 0),
38 SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 8 * 1024,
39 CFG_INIT_RAM_ADDR + 8 * 1024,
40 MAS3_SX | MAS3_SW | MAS3_SR, 0,
41 0, 0, BOOKE_PAGESZ_4K, 0),
42 SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 12 * 1024,
43 CFG_INIT_RAM_ADDR + 12 * 1024,
44 MAS3_SX | MAS3_SW | MAS3_SR, 0,
45 0, 0, BOOKE_PAGESZ_4K, 0),
Kumar Gala3b558e22008-01-17 02:02:10 -060046
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +020047#ifndef CONFIG_TQM_BIGFLASH
Kumar Gala3b558e22008-01-17 02:02:10 -060048 /*
49 * TLB 0, 1: 128M Non-cacheable, guarded
50 * 0xf8000000 128M FLASH
51 * Out of reset this entry is only 4K.
52 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020053 SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
54 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
55 0, 1, BOOKE_PAGESZ_64M, 1),
56 SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x4000000,
57 CFG_FLASH_BASE + 0x4000000,
58 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
59 0, 0, BOOKE_PAGESZ_64M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -060060
61 /*
62 * TLB 2: 256M Non-cacheable, guarded
63 * 0x80000000 256M PCI1 MEM First half
64 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020065 SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
66 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
67 0, 2, BOOKE_PAGESZ_256M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -060068
69 /*
70 * TLB 3: 256M Non-cacheable, guarded
71 * 0x90000000 256M PCI1 MEM Second half
72 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020073 SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
74 CFG_PCI1_MEM_PHYS + 0x10000000,
75 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
76 0, 3, BOOKE_PAGESZ_256M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -060077
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +020078#ifdef CONFIG_PCIE1
79 /*
80 * TLB 4: 256M Non-cacheable, guarded
81 * 0xc0000000 256M PCI express MEM First half
82 */
83 SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
84 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
85 0, 4, BOOKE_PAGESZ_256M, 1),
86
87 /*
88 * TLB 5: 256M Non-cacheable, guarded
89 * 0xd0000000 256M PCI express MEM Second half
90 */
91 SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE + 0x10000000,
92 CFG_PCIE1_MEM_BASE + 0x10000000,
93 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
94 0, 5, BOOKE_PAGESZ_256M, 1),
95#else /* !CONFIG_PCIE */
Kumar Gala3b558e22008-01-17 02:02:10 -060096 /*
97 * TLB 4: 256M Non-cacheable, guarded
98 * 0xc0000000 256M Rapid IO MEM First half
99 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200100 SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
101 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
102 0, 4, BOOKE_PAGESZ_256M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -0600103
104 /*
105 * TLB 5: 256M Non-cacheable, guarded
106 * 0xd0000000 256M Rapid IO MEM Second half
107 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200108 SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE + 0x10000000,
109 CFG_RIO_MEM_BASE + 0x10000000,
110 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
111 0, 5, BOOKE_PAGESZ_256M, 1),
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200112#endif /* CONFIG_PCIE */
Kumar Gala3b558e22008-01-17 02:02:10 -0600113
114 /*
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200115 * TLB 6: 64M Non-cacheable, guarded
116 * 0xe0000000 1M CCSRBAR
117 * 0xe2000000 16M PCI1 IO
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200118 * 0xe3000000 16M CAN and NAND Flash
Kumar Gala3b558e22008-01-17 02:02:10 -0600119 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200120 SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
121 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
122 0, 6, BOOKE_PAGESZ_64M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -0600123
124 /*
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200125 * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
126 * 0x00000000 512M DDR System memory
Kumar Gala3b558e22008-01-17 02:02:10 -0600127 * Without SPD EEPROM configured DDR, this must be setup manually.
128 * Make sure the TLB count at the top of this table is correct.
129 * Likely it needs to be increased by two for these entries.
130 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200131 SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
132 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
133 0, 7, BOOKE_PAGESZ_256M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -0600134
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200135 SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
136 CFG_DDR_SDRAM_BASE + 0x10000000,
137 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
138 0, 8, BOOKE_PAGESZ_256M, 1),
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200139
140#ifdef CONFIG_PCIE1
141 /*
142 * TLB 9: 16M Non-cacheable, guarded
143 * 0xef000000 16M PCI express IO
144 */
145 SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
146 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
147 0, 9, BOOKE_PAGESZ_16M, 1),
148#endif /* CONFIG_PCIE */
149
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200150#else /* CONFIG_TQM_BIGFLASH */
151
152 /*
153 * TLB 0,1,2,3: 1G Non-cacheable, guarded
154 * 0xc0000000 1G FLASH
155 * Out of reset this entry is only 4K.
156 */
157 SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
158 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
159 0, 3, BOOKE_PAGESZ_256M, 1),
160 SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x10000000,
161 CFG_FLASH_BASE + 0x10000000,
162 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
163 0, 2, BOOKE_PAGESZ_256M, 1),
164 SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x20000000,
165 CFG_FLASH_BASE + 0x20000000,
166 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
167 0, 1, BOOKE_PAGESZ_256M, 1),
168 SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x30000000,
169 CFG_FLASH_BASE + 0x30000000,
170 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
171 0, 0, BOOKE_PAGESZ_256M, 1),
172
173 /*
174 * TLB 4: 256M Non-cacheable, guarded
175 * 0x80000000 256M PCI1 MEM First half
176 */
177 SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
178 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
179 0, 4, BOOKE_PAGESZ_256M, 1),
180
181 /*
182 * TLB 5: 256M Non-cacheable, guarded
183 * 0x90000000 256M PCI1 MEM Second half
184 */
185 SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
186 CFG_PCI1_MEM_PHYS + 0x10000000,
187 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
188 0, 5, BOOKE_PAGESZ_256M, 1),
189
190#ifdef CONFIG_PCIE1
191 /*
192 * TLB 6: 256M Non-cacheable, guarded
193 * 0xc0000000 256M PCI express MEM First half
194 */
195 SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
196 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
197 0, 6, BOOKE_PAGESZ_256M, 1),
198#else /* !CONFIG_PCIE */
199 /*
200 * TLB 6: 256M Non-cacheable, guarded
201 * 0xb0000000 256M Rapid IO MEM First half
202 */
203 SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
204 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
205 0, 6, BOOKE_PAGESZ_256M, 1),
206
207#endif /* CONFIG_PCIE */
208
209 /*
210 * TLB 7: 64M Non-cacheable, guarded
211 * 0xa0000000 1M CCSRBAR
212 * 0xa2000000 16M PCI1 IO
213 * 0xa3000000 16M CAN and NAND Flash
214 */
215 SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
216 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
217 0, 7, BOOKE_PAGESZ_64M, 1),
218
219 /*
220 * TLB 8+9: 512M DDR, cache disabled (needed for memory test)
221 * 0x00000000 512M DDR System memory
222 * Without SPD EEPROM configured DDR, this must be setup manually.
223 * Make sure the TLB count at the top of this table is correct.
224 * Likely it needs to be increased by two for these entries.
225 */
226 SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
227 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
228 0, 8, BOOKE_PAGESZ_256M, 1),
229
230 SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
231 CFG_DDR_SDRAM_BASE + 0x10000000,
232 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
233 0, 9, BOOKE_PAGESZ_256M, 1),
234
235#ifdef CONFIG_PCIE1
236 /*
237 * TLB 10: 16M Non-cacheable, guarded
238 * 0xaf000000 16M PCI express IO
239 */
240 SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
241 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
242 0, 10, BOOKE_PAGESZ_16M, 1),
243#endif /* CONFIG_PCIE */
244
245#endif /* CONFIG_TQM_BIGFLASH */
Kumar Gala3b558e22008-01-17 02:02:10 -0600246};
247
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200248int num_tlb_entries = ARRAY_SIZE (tlb_table);