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TsiChungLiewc8758102008-01-14 17:46:19 -06001/*
2 *
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <watchdog.h>
30
31#include <asm/immap.h>
32#include <asm/rtc.h>
33
34/*
35 * Breath some life into the CPU...
36 *
37 * Set up the memory map,
38 * initialize a bunch of registers,
39 * initialize the UPM's
40 */
41void cpu_init_f(void)
42{
43 volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
44 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
45 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
46 volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
47
48 /* Workaround, must place before fbcs */
49 pll->psr = 0x12;
50
51 scm1->mpr = 0x77777777;
52 scm1->pacra = 0;
53 scm1->pacrb = 0;
54 scm1->pacrc = 0;
55 scm1->pacrd = 0;
56 scm1->pacre = 0;
57 scm1->pacrf = 0;
58 scm1->pacrg = 0;
59 scm1->pacri = 0;
60
61#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
62 fbcs->csar0 = CFG_CS0_BASE;
63 fbcs->cscr0 = CFG_CS0_CTRL;
64 fbcs->csmr0 = CFG_CS0_MASK;
65#endif
66
67#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
68 fbcs->csar1 = CFG_CS1_BASE;
69 fbcs->cscr1 = CFG_CS1_CTRL;
70 fbcs->csmr1 = CFG_CS1_MASK;
71#endif
72
73#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
74 fbcs->csar2 = CFG_CS2_BASE;
75 fbcs->cscr2 = CFG_CS2_CTRL;
76 fbcs->csmr2 = CFG_CS2_MASK;
77#endif
78
79#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
80 fbcs->csar3 = CFG_CS3_BASE;
81 fbcs->cscr3 = CFG_CS3_CTRL;
82 fbcs->csmr3 = CFG_CS3_MASK;
83#endif
84
85#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
86 fbcs->csar4 = CFG_CS4_BASE;
87 fbcs->cscr4 = CFG_CS4_CTRL;
88 fbcs->csmr4 = CFG_CS4_MASK;
89#endif
90
91#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
92 fbcs->csar5 = CFG_CS5_BASE;
93 fbcs->cscr5 = CFG_CS5_CTRL;
94 fbcs->csmr5 = CFG_CS5_MASK;
95#endif
96
97#ifdef CONFIG_FSL_I2C
98 gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA;
99#endif
100
101 icache_enable();
102}
103
104/*
105 * initialize higher level parts of CPU like timers
106 */
107int cpu_init_r(void)
108{
TsiChung Liewbc3ccb12008-07-09 15:47:27 -0500109#ifdef CONFIG_MCFRTC
TsiChungLiewc8758102008-01-14 17:46:19 -0600110 volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
111 volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
112 u32 oscillator = CFG_RTC_OSCILLATOR;
113
114 rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF;
115 rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF;
116#endif
117
118 return (0);
119}
120
121void uart_port_conf(void)
122{
123 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
124
125 /* Setup Ports: */
126 switch (CFG_UART_PORT) {
127 case 0:
128 gpio->par_uart &=
129 (GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK);
130 gpio->par_uart |=
131 (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
132 break;
133 case 1:
134 gpio->par_uart &=
135 (GPIO_PAR_UART_U1TXD_MASK & GPIO_PAR_UART_U1RXD_MASK);
136 gpio->par_uart |=
137 (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
138 break;
139 case 2:
140 gpio->par_dspi &=
141 (GPIO_PAR_DSPI_SIN_MASK & GPIO_PAR_DSPI_SOUT_MASK);
142 gpio->par_dspi =
143 (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
144 break;
145 }
146}