blob: c011809b6fd4b2e19ea085fb116a04bea5aa98a2 [file] [log] [blame]
wdenk2d1a5372004-02-23 19:30:57 +00001/*
2 * Copyright (C) 2004 IMMS gGmbH <www.imms.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 * author(s): Thomas Elste, <info@elste.org>
20 * (some parts derived from uCLinux Netarm Ethernet Driver)
21 */
22
23
24#include <common.h>
25#include <command.h>
26#include <net.h>
27#include "netarm_eth.h"
28#include <asm/arch/netarm_registers.h>
29
wdenk2d1a5372004-02-23 19:30:57 +000030static int na_mii_poll_busy (void);
31
32static void na_get_mac_addr (void)
33{
34 unsigned short p[3];
35 char *m_addr;
36 char ethaddr[20];
37
38 m_addr = (char *) p;
39
40 p[0] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_1);
41 p[1] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_2);
42 p[2] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_3);
43
44 sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
45 m_addr[0], m_addr[1],
46 m_addr[2], m_addr[3], m_addr[4], m_addr[5]);
47
48 printf ("HW-MAC Address: %s\n", ethaddr);
49
50 /* set env, todo: check if already an adress is set */
51 setenv ("ethaddr", ethaddr);
52}
53
wdenk2d1a5372004-02-23 19:30:57 +000054static void na_mii_write (int reg, int value)
55{
56 int mii_addr;
57
58 /* Select register */
59 mii_addr = CFG_ETH_PHY_ADDR + reg;
60 SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
61 /* Write value */
62 SET_EADDR (NETARM_ETH_MII_WRITE, value);
63 na_mii_poll_busy ();
64}
65
66static unsigned int na_mii_read (int reg)
67{
68 int mii_addr, val;
69
70 /* Select register */
71 mii_addr = CFG_ETH_PHY_ADDR + reg;
72 SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
73 /* do one management cycle */
74 SET_EADDR (NETARM_ETH_MII_CMD,
75 GET_EADDR (NETARM_ETH_MII_CMD) | NETARM_ETH_MIIC_RSTAT);
76 na_mii_poll_busy ();
77 /* Return read value */
78 val = GET_EADDR (NETARM_ETH_MII_READ);
79 return val;
80}
81
82static int na_mii_poll_busy (void)
83{
84 /* arm simple, non interrupt dependent timer */
85 reset_timer_masked ();
86 while (get_timer_masked () < NA_MII_POLL_BUSY_DELAY) {
87 if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) {
88 return 1;
89 }
90 }
91 printf ("na_mii_busy timeout\n");
92 return (0);
93}
94
95static int na_mii_identify_phy (void)
96{
97 int id_reg_a = 0;
98
99 /* get phy id register */
100 id_reg_a = na_mii_read (MII_PHY_ID);
101
102 if (id_reg_a == 0x0043) {
103 /* This must be an Enable or a Lucent LU3X31 PHY chip */
104 return 1;
105 } else if (id_reg_a == 0x0013) {
106 /* it is an Intel LXT971A */
107 return 1;
108 }
109 return (0);
110}
111
112static int na_mii_negotiate (void)
113{
114 int i = 0;
115
116 /* Enable auto-negotiation */
117 na_mii_write (MII_PHY_AUTONEGADV, 0x01e1);
118 /* FIXME: 0x01E1 is 100Mb half and full duplex, 0x0061 is 10Mb only */
119 /* Restart auto-negotiation */
120 na_mii_write (MII_PHY_CONTROL, 0x1200);
121
122 /* status register is 0xffff after setting the autoneg restart bit */
123 while (na_mii_read (MII_PHY_STATUS) == 0xffff) {
124 i++;
125 }
126
127 /* na_mii_read uses the timer already, so we can't use it again for
128 timeout checking.
129 Instead we just try some times.
130 */
131 for (i = 0; i < 40000; i++) {
132 if ((na_mii_read (MII_PHY_STATUS) & 0x0024) == 0x0024) {
133 return 0;
134 }
135 }
136 /*
137 printf("*Warning* autonegotiation timeout, status: 0x%x\n",na_mii_read(MII_PHY_STATUS));
138 */
139 return (1);
140}
141
142static unsigned int na_mii_check_speed (void)
143{
144 unsigned int status;
145
146 /* Read Status register */
147 status = na_mii_read (MII_PHY_STATUS);
148 /* Check link status. If 0, default to 100 Mbps. */
149 if ((status & 0x0004) == 0) {
150 printf ("*Warning* no link detected, set default speed to 100Mbs\n");
151 return 1;
152 } else {
153 if ((na_mii_read (17) & 0x4000) != 0) {
154 printf ("100Mbs link detected\n");
155 return 1;
156 } else {
157 printf ("10Mbs link detected\n");
158 return 0;
159 }
160 }
161 return 0;
162}
163
164static int reset_eth (void)
165{
166 int pt;
167
168 na_get_mac_addr ();
169 pt = na_mii_identify_phy ();
170
171 /* reset the phy */
172 na_mii_write (MII_PHY_CONTROL, 0x8000);
173 reset_timer_masked ();
174 while (get_timer_masked () < NA_MII_NEGOTIATE_DELAY) {
175 if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) {
176 break;
177 }
178 }
179 if (get_timer_masked () >= NA_MII_NEGOTIATE_DELAY)
180 printf ("phy reset timeout\n");
181
182 /* set the PCS reg */
183 SET_EADDR (NETARM_ETH_PCS_CFG, NETARM_ETH_PCSC_CLKS_25M |
184 NETARM_ETH_PCSC_ENJAB | NETARM_ETH_PCSC_NOCFR);
185
186 na_mii_negotiate ();
187 na_mii_check_speed ();
188
189 /* Delay 10 millisecond. (Maybe this should be 1 second.) */
190 udelay (10000);
191
192 /* Turn receive on.
193 Enable statistics register autozero on read.
194 Do not insert MAC address on transmit.
195 Do not enable special test modes. */
196 SET_EADDR (NETARM_ETH_STL_CFG,
197 (NETARM_ETH_STLC_AUTOZ | NETARM_ETH_STLC_RXEN));
198
199 /* Set the inter-packet gap delay to 0.96us for MII.
200 The NET+ARM H/W Reference Guide indicates that the Back-to-back IPG
201 Gap Timer Register should be set to 0x15 and the Non Back-to-back IPG
202 Gap Timer Register should be set to 0x00000C12 for the MII PHY. */
203 SET_EADDR (NETARM_ETH_B2B_IPG_GAP_TMR, 0x15);
204 SET_EADDR (NETARM_ETH_NB2B_IPG_GAP_TMR, 0x00000C12);
205
206 /* Add CRC to end of packets.
207 Pad packets to minimum length of 64 bytes.
208 Allow unlimited length transmit packets.
209 Receive all broadcast packets.
210 NOTE: Multicast addressing is NOT enabled here currently. */
211 SET_EADDR (NETARM_ETH_MAC_CFG,
212 (NETARM_ETH_MACC_CRCEN |
213 NETARM_ETH_MACC_PADEN | NETARM_ETH_MACC_HUGEN));
214 SET_EADDR (NETARM_ETH_SAL_FILTER, NETARM_ETH_SALF_BROAD);
215
216 /* enable fifos */
217 SET_EADDR (NETARM_ETH_GEN_CTRL,
218 (NETARM_ETH_GCR_ERX | NETARM_ETH_GCR_ETX));
219
220 return (0);
221}
222
223
224extern int eth_init (bd_t * bd)
225{
226 reset_eth ();
227 return 0;
228}
229
230extern void eth_halt (void)
231{
232 SET_EADDR (NETARM_ETH_GEN_CTRL, 0);
233}
234
235/* Get a data block via Ethernet */
236extern int eth_rx (void)
237{
238 int i;
239 unsigned short rxlen;
240 unsigned int *addr;
241 unsigned int rxstatus, lastrxlen;
242 char *pa;
243
244 /* RXBR is 1, data block was received */
245 if ((GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXBR) == 0)
246 return 0;
247
248 /* get status register and the length of received block */
249 rxstatus = GET_EADDR (NETARM_ETH_RX_STAT);
250 rxlen = (rxstatus & NETARM_ETH_RXSTAT_SIZE) >> 16;
251
252 if (rxlen == 0)
253 return 0;
254
255 /* clear RXBR to make fifo available */
256 SET_EADDR (NETARM_ETH_GEN_STAT,
257 GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_RXBR);
258
259 /* clear TXBC to make fifo available */
260 /* According to NETARM50 data manual you just have to clear
261 RXBR but that has no effect. Only after clearing TXBC the
262 Fifo becomes readable. */
263 SET_EADDR (NETARM_ETH_GEN_STAT,
264 GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_TXBC);
265
266 addr = (unsigned int *) NetRxPackets[0];
267 pa = (char *) NetRxPackets[0];
268
269 /* read the fifo */
270 for (i = 0; i < rxlen / 4; i++) {
271 *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1);
272 addr++;
273 }
274
275 if (GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXREGR) {
276 /* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */
277 lastrxlen =
278 (GET_EADDR (NETARM_ETH_GEN_STAT) &
279 NETARM_ETH_GST_RXFDB) >> 28;
280 *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1);
281 switch (lastrxlen) {
282 case 1:
283 *addr &= 0xff000000;
284 break;
285 case 2:
286 *addr &= 0xffff0000;
287 break;
288 case 3:
289 *addr &= 0xffffff00;
290 break;
291 }
292 }
293
294 /* Pass the packet up to the protocol layers. */
295 NetReceive (NetRxPackets[0], rxlen);
296
297 return rxlen;
298}
299
300/* Send a data block via Ethernet. */
301extern int eth_send (volatile void *packet, int length)
302{
303 int i, length32;
304 char *pa;
305 unsigned int *pa32, lastp = 0, rest;
306
307 pa = (char *) packet;
308 pa32 = (unsigned int *) packet;
309 length32 = length / 4;
310 rest = length % 4;
311
312 /* make sure there's no garbage in the last word */
313 switch (rest) {
314 case 0:
315 lastp = pa32[length32];
316 length32--;
317 break;
318 case 1:
319 lastp = pa32[length32] & 0x000000ff;
320 break;
321 case 2:
322 lastp = pa32[length32] & 0x0000ffff;
323 break;
324 case 3:
325 lastp = pa32[length32] & 0x00ffffff;
326 break;
327 }
328
329 /* write to the fifo */
330 for (i = 0; i < length32; i++)
331 SET_EADDR (NETARM_ETH_FIFO_DAT1, pa32[i]);
332
333 /* the last word is written to an extra register, this
334 starts the transmission */
335 SET_EADDR (NETARM_ETH_FIFO_DAT2, lastp);
336
337 /* NETARM_ETH_TXSTAT_TXOK should be checked, to know if the transmission
338 went fine. But we can't use the timer for a timeout loop because
339 of it is used already in upper layers. So we just try some times. */
340 i = 0;
341 while (i < 50000) {
342 if ((GET_EADDR (NETARM_ETH_TX_STAT) & NETARM_ETH_TXSTAT_TXOK)
343 == NETARM_ETH_TXSTAT_TXOK)
344 return 0;
345 i++;
346 }
347
348 printf ("eth_send timeout\n");
349 return 1;
350}