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wdenk2d1a5372004-02-23 19:30:57 +00001/*
2 * (C) Copyright 2004
3 * IMMS, gGmbH <www.imms.de>
4 * Thomas Elste <info@elste.org>
5 *
6 * Configuation settings for ModNET50 board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
wdenk2d1a5372004-02-23 19:30:57 +000031 * High Level Configuration Options
32 * (easy to change)
33 */
34#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
35#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
36#define CONFIG_NETARM /* it's a Netsiclicon NET+ARM */
37#undef CONFIG_NETARM_NET40_REV2 /* it's a Net+40 Rev. 2 */
38#undef CONFIG_NETARM_NET40_REV4 /* it's a Net+40 Rev. 4 */
39#define CONFIG_NETARM_NET50 /* it's a Net+50 */
40
41#define CONFIG_MODNET50 1 /* on an ModNET50 Board */
42
43#undef CONFIG_USE_IRQ /* don't need them anymore */
44
45/*
46 * Size of malloc() pool
47 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020048#define CFG_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenk2d1a5372004-02-23 19:30:57 +000049#define CFG_GBL_DATA_SIZE 128
50
51/*
52 * Hardware drivers
53 */
54#define CONFIG_DRIVER_NETARMETH 1
55
56/*
57 * select serial console configuration
58 */
59#define CONFIG_SERIAL1 1 /* we use Serial line 1 */
60
61/* allow to overwrite serial and ethaddr */
62#define CONFIG_ENV_OVERWRITE
63
64#define CONFIG_BAUDRATE 38400
65
Jon Loeliger2fd90ce2007-07-09 21:48:26 -050066/*
67 * BOOTP options
68 */
69#define CONFIG_BOOTP_SUBNETMASK
70#define CONFIG_BOOTP_GATEWAY
71#define CONFIG_BOOTP_HOSTNAME
72#define CONFIG_BOOTP_BOOTPATH
73#define CONFIG_BOOTP_BOOTFILESIZE
wdenk2d1a5372004-02-23 19:30:57 +000074
wdenk2d1a5372004-02-23 19:30:57 +000075
Jon Loeliger5dc11a52007-07-04 22:33:01 -050076/*
77 * Command line configuration.
78 */
79#include <config_cmd_default.h>
80
81#define CONFIG_CMD_JFFS2
82
wdenk2d1a5372004-02-23 19:30:57 +000083
84#define CONFIG_NETMASK 255.255.255.0
85#define CONFIG_IPADDR 192.168.30.2
86#define CONFIG_SERVERIP 192.168.30.122
87#define CFG_ETH_PHY_ADDR 0x100
88#define CONFIG_CMDLINE_TAG /* submit bootargs to kernel */
89
90/*#define CONFIG_BOOTDELAY 10*/
91/* args and cmd for uClinux-image @ 0x10020000, ramdisk-image @ 0x100a0000 */
92#define CONFIG_BOOTCOMMAND "bootm 0x10020000 0x100a0000"
Wolfgang Denk53677ef2008-05-20 16:00:29 +020093#define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K " \
94 "root=/dev/ram keepinitrd"
wdenk2d1a5372004-02-23 19:30:57 +000095
Jon Loeliger5dc11a52007-07-04 22:33:01 -050096#if defined(CONFIG_CMD_KGDB)
wdenk2d1a5372004-02-23 19:30:57 +000097#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
98#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
99#endif
100
101/*
102 * Miscellaneous configurable options
103 */
104#define CFG_LONGHELP /* undef to save memory */
105#define CFG_PROMPT "modnet50 # " /* Monitor Command Prompt */
106#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
107#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
108#define CFG_MAXARGS 16 /* max number of command args */
109#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
110
111#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
112#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
113
114#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
115
116#define CFG_LOAD_ADDR 0x00500000 /* default load address */
117
118#define CFG_HZ 900 /* decrementer freq: 2 kHz */
119
120 /* valid baudrates */
121#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
122
123/*-----------------------------------------------------------------------
124 * Stack sizes
125 *
126 * The stack sizes are set up in start.S using the settings below
127*/
128#define CONFIG_STACKSIZE (128*1024) /* regular stack */
129#ifdef CONFIG_USE_IRQ
130#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
131#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
132#endif
133
134/*-----------------------------------------------------------------------
135 * Physical Memory Map
136 */
137#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */
138#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
139#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
140#define PHYS_SDRAM_2 0x01000000 /* SDRAM Bank #1 */
141#define PHYS_SDRAM_2_SIZE 0x01000000 /* 16 MB */
142
143#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */
144#define PHYS_FLASH_1_SIZE 0x00200000 /* 2 MB (one chip only, 16bit access) */
145
146#define PHYS_FLASH_2 0x10200001
147#define PHYS_FLASH_2_SIZE 0x00200000
148
149#define CONFIG_NETARM_EEPROM
150/* #ifdef CONFIG_NETARM_EEPROM */
151#define PHYS_NVRAM_1 0x20000000 /* EEPROM Bank #1 */
152#define PHYS_NVRAM_SIZE 0x00002000 /* 8 KB */
153/* #endif */
154
155#define PHYS_EXT_1 0x30000000 /* Extensions Bank #1 */
156#define PHYS_EXT_SIZE 0x01000000 /* 32 MB memory mapped I/O */
157
158#define CFG_FLASH_BASE PHYS_FLASH_1
159#define CFG_FLASH_SIZE PHYS_FLASH_1_SIZE
160
161/*-----------------------------------------------------------------------
162 * FLASH and environment organization
163 */
164#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
165#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
166#define CFG_MAIN_SECT_SIZE 0x00010000 /* main size of sectors on one chip */
167
168/* timeout values are in ticks */
169#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
170#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
171
172/* environment settings */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200173#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200174#undef CONFIG_ENV_IS_NOWHERE
wdenk2d1a5372004-02-23 19:30:57 +0000175
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200176#define CONFIG_ENV_ADDR 0x1001C000 /* environment start address */
177#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
178#define CONFIG_ENV_SIZE 0x4000 /* max size for environment */
wdenk2d1a5372004-02-23 19:30:57 +0000179
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200180/*
181 * JFFS2 partitions
182 *
183 */
184/* No command line, one static partition, whole device */
185#undef CONFIG_JFFS2_CMDLINE
186#define CONFIG_JFFS2_DEV "nor0"
187#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
188#define CONFIG_JFFS2_PART_OFFSET 0x00080000
189
190/* mtdparts command line support */
191/* Note: fake mtd_id used, no linux mtd map file */
192/*
193#define CONFIG_JFFS2_CMDLINE
194#define MTDIDS_DEFAULT "nor0=modnet50-0"
195#define MTDPARTS_DEFAULT "mtdparts=modnet50-0:-@512k(jffs2)"
196*/
wdenk2d1a5372004-02-23 19:30:57 +0000197
198#endif /* __CONFIG_H */