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wdenka56bd922004-06-06 23:13:55 +00001/*
wdenk1eaeb582004-06-08 00:22:43 +00002 * (C) Copyright 2003-2004
wdenka56bd922004-06-06 23:13:55 +00003 * MPC Data Limited (http://www.mpc-data.co.uk)
4 * Dave Peverley <dpeverley at mpc-data.co.uk>
5 *
6 * Configuation settings for the TI OMAP Perseus 2 board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk1eaeb582004-06-08 00:22:43 +000018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenka56bd922004-06-06 23:13:55 +000019 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
wdenka56bd922004-06-06 23:13:55 +000030/* allow to overwrite serial and ethaddr */
31#define CONFIG_ENV_OVERWRITE
32
wdenka56bd922004-06-06 23:13:55 +000033/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
wdenk1eaeb582004-06-08 00:22:43 +000038#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
39#define CONFIG_OMAP 1 /* in a TI OMAP core */
40#define CONFIG_OMAP730 1 /* which is in a 730 */
41#define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */
wdenka56bd922004-06-06 23:13:55 +000042
wdenk1eaeb582004-06-08 00:22:43 +000043/*
44 * Input clock of PLL
45 * The OMAP730 Perseus 2 has 13MHz input clock
wdenka56bd922004-06-06 23:13:55 +000046 */
47
wdenk1eaeb582004-06-08 00:22:43 +000048#define CONFIG_SYS_CLK_FREQ 13000000
wdenka56bd922004-06-06 23:13:55 +000049
wdenk1eaeb582004-06-08 00:22:43 +000050#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
wdenka56bd922004-06-06 23:13:55 +000051
52#define CONFIG_MISC_INIT_R
53
wdenk1eaeb582004-06-08 00:22:43 +000054#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
wdenka56bd922004-06-06 23:13:55 +000055#define CONFIG_SETUP_MEMORY_TAGS 1
56
wdenka56bd922004-06-06 23:13:55 +000057/*
58 * Size of malloc() pool
59 */
60
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020061#define CFG_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenk1eaeb582004-06-08 00:22:43 +000062#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenka56bd922004-06-06 23:13:55 +000063
64/*
65 * Hardware drivers
66 */
67
68#define CONFIG_DRIVER_LAN91C96
wdenk1eaeb582004-06-08 00:22:43 +000069#define CONFIG_LAN91C96_BASE 0x04000300
wdenka56bd922004-06-06 23:13:55 +000070#define CONFIG_LAN91C96_EXT_PHY
71
wdenka56bd922004-06-06 23:13:55 +000072/*
73 * NS16550 Configuration
74 */
75
76#define CFG_NS16550
77#define CFG_NS16550_SERIAL
wdenk1eaeb582004-06-08 00:22:43 +000078#define CFG_NS16550_REG_SIZE (1)
79#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
80#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
81 * on perseus */
wdenka56bd922004-06-06 23:13:55 +000082
83/*
84 * select serial console configuration
85 */
86
wdenk1eaeb582004-06-08 00:22:43 +000087#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */
wdenka56bd922004-06-06 23:13:55 +000088
wdenk1eaeb582004-06-08 00:22:43 +000089#define CONFIG_CONS_INDEX 1
90#define CONFIG_BAUDRATE 115200
91#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenka56bd922004-06-06 23:13:55 +000092
wdenka56bd922004-06-06 23:13:55 +000093
wdenk1eaeb582004-06-08 00:22:43 +000094/*
Jon Loeligera5cb2302007-07-04 22:33:13 -050095 * Command line configuration.
wdenka56bd922004-06-06 23:13:55 +000096 */
Jon Loeligera5cb2302007-07-04 22:33:13 -050097#include <config_cmd_default.h>
wdenka56bd922004-06-06 23:13:55 +000098
Jon Loeligera5cb2302007-07-04 22:33:13 -050099#define CONFIG_CMD_DHCP
100
101
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500102/*
103 * BOOTP options
104 */
105#define CONFIG_BOOTP_SUBNETMASK
106#define CONFIG_BOOTP_GATEWAY
107#define CONFIG_BOOTP_HOSTNAME
108#define CONFIG_BOOTP_BOOTPATH
109
Jon Loeligera5cb2302007-07-04 22:33:13 -0500110
wdenka56bd922004-06-06 23:13:55 +0000111#include <configs/omap730.h>
112#include <configs/h2_p2_dbg_board.h>
113
wdenk1eaeb582004-06-08 00:22:43 +0000114#define CONFIG_BOOTDELAY 3
115#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
wdenka56bd922004-06-06 23:13:55 +0000116
wdenk1eaeb582004-06-08 00:22:43 +0000117#define CONFIG_LOADADDR 0x10000000
wdenka56bd922004-06-06 23:13:55 +0000118
119#define CONFIG_ETHADDR
wdenk1eaeb582004-06-08 00:22:43 +0000120#define CONFIG_NETMASK 255.255.255.0
121#define CONFIG_IPADDR 192.168.0.23
122#define CONFIG_SERVERIP 192.150.0.100
123#define CONFIG_BOOTFILE "uImage" /* File to load */
wdenka56bd922004-06-06 23:13:55 +0000124
Jon Loeligera5cb2302007-07-04 22:33:13 -0500125#if defined(CONFIG_CMD_KGDB)
wdenk1eaeb582004-06-08 00:22:43 +0000126#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */
127#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */
wdenka56bd922004-06-06 23:13:55 +0000128#endif
129
wdenka56bd922004-06-06 23:13:55 +0000130/*
131 * Miscellaneous configurable options
132 */
133
wdenk1eaeb582004-06-08 00:22:43 +0000134#define CFG_LONGHELP /* undef to save memory */
135#define CFG_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */
136#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenka56bd922004-06-06 23:13:55 +0000137/* Print Buffer Size */
wdenk1eaeb582004-06-08 00:22:43 +0000138#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
139#define CFG_MAXARGS 16 /* max number of command args */
140#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
wdenka56bd922004-06-06 23:13:55 +0000141
wdenk1eaeb582004-06-08 00:22:43 +0000142#define CFG_MEMTEST_START 0x10000000 /* memtest works on */
143#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
wdenka56bd922004-06-06 23:13:55 +0000144
wdenk1eaeb582004-06-08 00:22:43 +0000145#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
wdenka56bd922004-06-06 23:13:55 +0000146
wdenk1eaeb582004-06-08 00:22:43 +0000147#define CFG_LOAD_ADDR 0x10000000 /* default load address */
wdenka56bd922004-06-06 23:13:55 +0000148
wdenk1eaeb582004-06-08 00:22:43 +0000149/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
150 * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
wdenka56bd922004-06-06 23:13:55 +0000151 * local divisor.
152 */
153
wdenk1eaeb582004-06-08 00:22:43 +0000154#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */
155#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
156#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
wdenka56bd922004-06-06 23:13:55 +0000157
158/*-----------------------------------------------------------------------
159 * Stack sizes
160 *
161 * The stack sizes are set up in start.S using the settings below
162 */
163
wdenk1eaeb582004-06-08 00:22:43 +0000164#define CONFIG_STACKSIZE (128*1024) /* regular stack */
wdenka56bd922004-06-06 23:13:55 +0000165#ifdef CONFIG_USE_IRQ
wdenk1eaeb582004-06-08 00:22:43 +0000166#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
167#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
wdenka56bd922004-06-06 23:13:55 +0000168#endif
169
wdenka56bd922004-06-06 23:13:55 +0000170/*-----------------------------------------------------------------------
171 * Physical Memory Map
172 */
173
wdenk1eaeb582004-06-08 00:22:43 +0000174#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
175#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
176#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
wdenka56bd922004-06-06 23:13:55 +0000177
178#if defined(CONFIG_CS0_BOOT)
wdenk1eaeb582004-06-08 00:22:43 +0000179#define PHYS_FLASH_1 0x0C000000
wdenka56bd922004-06-06 23:13:55 +0000180#elif defined(CONFIG_CS3_BOOT)
wdenk1eaeb582004-06-08 00:22:43 +0000181#define PHYS_FLASH_1 0x00000000
wdenka56bd922004-06-06 23:13:55 +0000182#else
183#error Unknown Boot Chip-Select number
184#endif
185
wdenk1eaeb582004-06-08 00:22:43 +0000186#define CFG_FLASH_BASE PHYS_FLASH_1
wdenka56bd922004-06-06 23:13:55 +0000187
188/*-----------------------------------------------------------------------
189 * FLASH and environment organization
190 */
191
wdenk1eaeb582004-06-08 00:22:43 +0000192#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
193#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
194#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
wdenka56bd922004-06-06 23:13:55 +0000195/* addr of environment */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200196#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0x020000)
wdenka56bd922004-06-06 23:13:55 +0000197
198/* timeout values are in ticks */
wdenk1eaeb582004-06-08 00:22:43 +0000199#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
200#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
wdenka56bd922004-06-06 23:13:55 +0000201
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200202#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200203#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
204#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
wdenka56bd922004-06-06 23:13:55 +0000205
wdenk1eaeb582004-06-08 00:22:43 +0000206#endif /* ! __CONFIG_H */