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Michal Simeka81186f2019-11-25 08:38:25 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU208
4 *
Michal Simek447fb8d2021-05-31 09:50:01 +02005 * (C) Copyright 2017 - 2021, Xilinx, Inc.
Michal Simeka81186f2019-11-25 08:38:25 +01006 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
Michal Simekbd008492021-05-10 13:14:02 +020016#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
Michal Simeka81186f2019-11-25 08:38:25 +010017#include <dt-bindings/phy/phy.h>
18
19/ {
20 model = "ZynqMP ZCU208 RevA";
21 compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp";
22
23 aliases {
24 ethernet0 = &gem3;
Michal Simeka81186f2019-11-25 08:38:25 +010025 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 mmc0 = &sdhci1;
Michal Simek531abcb2021-06-03 11:46:50 +020028 nvmem0 = &eeprom;
Michal Simeka81186f2019-11-25 08:38:25 +010029 rtc0 = &rtc;
30 serial0 = &uart0;
31 serial1 = &dcc;
32 spi0 = &qspi;
33 usb0 = &usb0;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
Michal Simeka81186f2019-11-25 08:38:25 +010039 };
40
41 memory@0 {
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
44 };
45
46 gpio-keys {
47 compatible = "gpio-keys";
48 autorepeat;
49 sw19 {
50 label = "sw19";
51 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
52 linux,code = <KEY_DOWN>;
Michal Simekf695e1c2020-02-18 12:06:14 +010053 wakeup-source;
Michal Simeka81186f2019-11-25 08:38:25 +010054 autorepeat;
55 };
56 };
57
58 leds {
59 compatible = "gpio-leds";
60 heartbeat_led {
61 label = "heartbeat";
62 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
63 linux,default-trigger = "heartbeat";
64 };
65 };
66
67 ina226-vccint {
68 compatible = "iio-hwmon";
69 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
70 };
71 ina226-vccint-io-bram-ps {
72 compatible = "iio-hwmon";
73 io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
74 };
75 ina226-vcc1v8 {
76 compatible = "iio-hwmon";
77 io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
78 };
79 ina226-vcc1v2 {
80 compatible = "iio-hwmon";
81 io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
82 };
83 ina226-vadj-fmc {
84 compatible = "iio-hwmon";
85 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
86 };
87 ina226-mgtavcc {
88 compatible = "iio-hwmon";
89 io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
90 };
91 ina226-mgt1v2 {
92 compatible = "iio-hwmon";
93 io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
94 };
95 ina226-mgt1v8 {
96 compatible = "iio-hwmon";
97 io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
98 };
99 ina226-vccint-ams {
100 compatible = "iio-hwmon";
101 io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
102 };
103 ina226-dac-avtt {
104 compatible = "iio-hwmon";
105 io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
106 };
107 ina226-dac-avccaux {
108 compatible = "iio-hwmon";
109 io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
110 };
111 ina226-adc-avcc {
112 compatible = "iio-hwmon";
113 io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
114 };
115 ina226-adc-avccaux {
116 compatible = "iio-hwmon";
117 io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
118 };
119 ina226-dac-avcc {
120 compatible = "iio-hwmon";
121 io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
122 };
Michal Simekce906542020-11-26 14:25:02 +0100123
124 /* 48MHz reference crystal */
125 ref48: ref48M {
126 compatible = "fixed-clock";
127 #clock-cells = <0>;
128 clock-frequency = <48000000>;
129 };
Michal Simeka81186f2019-11-25 08:38:25 +0100130};
131
132&dcc {
133 status = "okay";
134};
135
136&fpd_dma_chan1 {
137 status = "okay";
138};
139
140&fpd_dma_chan2 {
141 status = "okay";
142};
143
144&fpd_dma_chan3 {
145 status = "okay";
146};
147
148&fpd_dma_chan4 {
149 status = "okay";
150};
151
152&fpd_dma_chan5 {
153 status = "okay";
154};
155
156&fpd_dma_chan6 {
157 status = "okay";
158};
159
160&fpd_dma_chan7 {
161 status = "okay";
162};
163
164&fpd_dma_chan8 {
165 status = "okay";
166};
167
168&gem3 {
169 status = "okay";
170 phy-handle = <&phy0>;
171 phy-mode = "rgmii-id";
172 phy0: ethernet-phy@c {
173 reg = <0xc>;
174 ti,rx-internal-delay = <0x8>;
175 ti,tx-internal-delay = <0xa>;
176 ti,fifo-depth = <0x1>;
177 ti,dp83867-rxctrl-strap-quirk;
178 };
179};
180
181&gpio {
182 status = "okay";
183 gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
184 "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
185 "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
186 "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
187 "", "", "BUTTON", "LED", "", /* 20 - 24 */
188 "", "PMU_INPUT", "", "", "", /* 25 - 29 */
189 "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
190 "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
191 "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */
192 "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
193 "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
194 "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
195 "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
196 "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
197 "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
198 "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
199 "", "", /* 78 - 79 */
200 "", "", "", "", "", /* 80 - 84 */
201 "", "", "", "", "", /* 85 -89 */
202 "", "", "", "", "", /* 90 - 94 */
203 "", "", "", "", "", /* 95 - 99 */
204 "", "", "", "", "", /* 100 - 104 */
205 "", "", "", "", "", /* 105 - 109 */
206 "", "", "", "", "", /* 110 - 114 */
207 "", "", "", "", "", /* 115 - 119 */
208 "", "", "", "", "", /* 120 - 124 */
209 "", "", "", "", "", /* 125 - 129 */
210 "", "", "", "", "", /* 130 - 134 */
211 "", "", "", "", "", /* 135 - 139 */
212 "", "", "", "", "", /* 140 - 144 */
213 "", "", "", "", "", /* 145 - 149 */
214 "", "", "", "", "", /* 150 - 154 */
215 "", "", "", "", "", /* 155 - 159 */
216 "", "", "", "", "", /* 160 - 164 */
217 "", "", "", "", "", /* 165 - 169 */
218 "", "", "", ""; /* 170 - 174 */
219};
220
221&i2c0 {
222 status = "okay";
223 clock-frequency = <400000>;
Michal Simekbd008492021-05-10 13:14:02 +0200224 pinctrl-names = "default", "gpio";
225 pinctrl-0 = <&pinctrl_i2c0_default>;
226 pinctrl-1 = <&pinctrl_i2c0_gpio>;
227 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
228 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
Michal Simeka81186f2019-11-25 08:38:25 +0100229
230 tca6416_u15: gpio@20 { /* u15 */
231 compatible = "ti,tca6416";
232 reg = <0x20>;
233 gpio-controller; /* interrupt not connected */
234 #gpio-cells = <2>;
235 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */
236 "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
237 "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
238 "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
239 };
240
241 i2c-mux@75 { /* u17 */
242 compatible = "nxp,pca9544";
243 #address-cells = <1>;
244 #size-cells = <0>;
245 reg = <0x75>;
246 i2c@0 {
247 #address-cells = <1>;
248 #size-cells = <0>;
249 reg = <0>;
250 /* PS_PMBUS */
251 /* PMBUS_ALERT done via pca9544 */
252 vccint: ina226@40 { /* u65 */
253 compatible = "ti,ina226";
254 #io-channel-cells = <1>;
255 label = "ina226-vccint";
256 reg = <0x40>;
257 shunt-resistor = <5000>;
258 };
259 vccint_io_bram_ps: ina226@41 { /* u57 */
260 compatible = "ti,ina226";
261 #io-channel-cells = <1>;
262 label = "ina226-vccint-io-bram-ps";
263 reg = <0x41>;
264 shunt-resistor = <5000>;
265 };
266 vcc1v8: ina226@42 { /* u60 */
267 compatible = "ti,ina226";
268 #io-channel-cells = <1>;
269 label = "ina226-vcc1v8";
270 reg = <0x42>;
271 shunt-resistor = <2000>;
272 };
273 vcc1v2: ina226@43 { /* u58 */
274 compatible = "ti,ina226";
275 #io-channel-cells = <1>;
276 label = "ina226-vcc1v2";
277 reg = <0x43>;
278 shunt-resistor = <5000>;
279 };
280 vadj_fmc: ina226@45 { /* u62 */
281 compatible = "ti,ina226";
282 #io-channel-cells = <1>;
283 label = "ina226-vadj-fmc";
284 reg = <0x45>;
285 shunt-resistor = <5000>;
286 };
287 mgtavcc: ina226@46 { /* u67 */
288 compatible = "ti,ina226";
289 #io-channel-cells = <1>;
290 label = "ina226-mgtavcc";
291 reg = <0x46>;
292 shunt-resistor = <2000>;
293 };
294 mgt1v2: ina226@47 { /* u63 */
295 compatible = "ti,ina226";
296 #io-channel-cells = <1>;
297 label = "ina226-mgt1v2";
298 reg = <0x47>;
299 shunt-resistor = <5000>;
300 };
301 mgt1v8: ina226@48 { /* u64 */
302 compatible = "ti,ina226";
303 #io-channel-cells = <1>;
304 label = "ina226-mgt1v8";
305 reg = <0x48>;
306 shunt-resistor = <5000>;
307 };
308 vccint_ams: ina226@49 { /* u61 */
309 compatible = "ti,ina226";
310 #io-channel-cells = <1>;
311 label = "ina226-vccint-ams";
312 reg = <0x49>;
313 shunt-resistor = <5000>;
314 };
315 dac_avtt: ina226@4a { /* u59 */
316 compatible = "ti,ina226";
317 #io-channel-cells = <1>;
318 label = "ina226-dac-avtt";
319 reg = <0x4a>;
320 shunt-resistor = <5000>;
321 };
322 dac_avccaux: ina226@4b { /* u124 */
323 compatible = "ti,ina226";
324 #io-channel-cells = <1>;
325 label = "ina226-dac-avccaux";
326 reg = <0x4b>;
327 shunt-resistor = <5000>;
328 };
329 adc_avcc: ina226@4c { /* u75 */
330 compatible = "ti,ina226";
331 #io-channel-cells = <1>;
332 label = "ina226-adc-avcc";
333 reg = <0x4c>;
334 shunt-resistor = <5000>;
335 };
336 adc_avccaux: ina226@4d { /* u71 */
337 compatible = "ti,ina226";
338 #io-channel-cells = <1>;
339 label = "ina226-adc-avccaux";
340 reg = <0x4d>;
341 shunt-resistor = <5000>;
342 };
343 dac_avcc: ina226@4e { /* u77 */
344 compatible = "ti,ina226";
345 #io-channel-cells = <1>;
346 label = "ina226-dac-avcc";
347 reg = <0x4e>;
348 shunt-resistor = <5000>;
349 };
350 };
351 i2c@1 {
352 #address-cells = <1>;
353 #size-cells = <0>;
354 reg = <1>;
355 /* NC */
356 };
357 i2c@2 {
358 #address-cells = <1>;
359 #size-cells = <0>;
360 reg = <2>;
361 /* u104 - ir35215 0x10/0x40 */
362 /* u127 - ir38164 0x1b/0x4b */
363 /* u112 - ir38164 0x13/0x43 */
364 /* u123 - ir38164 0x1c/0x4c */
365
Michal Simek14c0fbb2020-03-30 11:35:38 +0200366 irps5401_44: irps5401@44 { /* IRPS5401 - u53 */
Michal Simeka81186f2019-11-25 08:38:25 +0100367 compatible = "infineon,irps5401";
368 reg = <0x44>; /* i2c addr 0x14 */
369 };
Michal Simek14c0fbb2020-03-30 11:35:38 +0200370 irps5401_45: irps5401@45 { /* IRPS5401 - u55 */
Michal Simeka81186f2019-11-25 08:38:25 +0100371 compatible = "infineon,irps5401";
372 reg = <0x45>; /* i2c addr 0x15 */
373 };
374 /* J21 header too */
375
376 };
377 i2c@3 {
378 #address-cells = <1>;
379 #size-cells = <0>;
380 reg = <3>;
381 /* SYSMON */
382 };
383 };
384 /* u38 MPS430 */
385};
386
387&i2c1 {
388 status = "okay";
389 clock-frequency = <400000>;
Michal Simekbd008492021-05-10 13:14:02 +0200390 pinctrl-names = "default", "gpio";
391 pinctrl-0 = <&pinctrl_i2c1_default>;
392 pinctrl-1 = <&pinctrl_i2c1_gpio>;
393 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
394 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
Michal Simeka81186f2019-11-25 08:38:25 +0100395
396 i2c-mux@74 {
397 compatible = "nxp,pca9548"; /* u20 */
398 #address-cells = <1>;
399 #size-cells = <0>;
400 reg = <0x74>;
Raviteja Narayanam486f25c2021-04-01 07:14:10 -0600401 i2c-mux-idle-disconnect;
Michal Simeka81186f2019-11-25 08:38:25 +0100402 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
403 i2c_eeprom: i2c@0 {
404 #address-cells = <1>;
405 #size-cells = <0>;
406 reg = <0>;
407 /*
408 * IIC_EEPROM 1kB memory which uses 256B blocks
409 * where every block has different address.
410 * 0 - 256B address 0x54
411 * 256B - 512B address 0x55
412 * 512B - 768B address 0x56
413 * 768B - 1024B address 0x57
414 */
415 eeprom: eeprom@54 { /* u21 */
416 compatible = "atmel,24c128";
417 reg = <0x54>;
418 };
419 };
420 i2c_si5341: i2c@1 {
421 #address-cells = <1>;
422 #size-cells = <0>;
423 reg = <1>;
424 si5341: clock-generator@36 { /* SI5341 - u43 */
Michal Simekce906542020-11-26 14:25:02 +0100425 compatible = "silabs,si5341";
Michal Simeka81186f2019-11-25 08:38:25 +0100426 reg = <0x36>;
Michal Simekce906542020-11-26 14:25:02 +0100427 #clock-cells = <2>;
428 #address-cells = <1>;
429 #size-cells = <0>;
430 clocks = <&ref48>;
431 clock-names = "xtal";
432 clock-output-names = "si5341";
Michal Simeka81186f2019-11-25 08:38:25 +0100433
Michal Simekce906542020-11-26 14:25:02 +0100434 si5341_2: out@2 {
435 /* refclk2 for PS-GT, used for USB3 */
436 reg = <2>;
Michal Simekfddff682021-03-11 13:34:02 +0100437 always-on;
Michal Simekce906542020-11-26 14:25:02 +0100438 };
439 si5341_3: out@3 {
440 /* refclk3 for PS-GT, used for SATA */
441 reg = <3>;
Michal Simekfddff682021-03-11 13:34:02 +0100442 always-on;
Michal Simekce906542020-11-26 14:25:02 +0100443 };
444 si5341_5: out@5 {
445 /* refclk5 PL CLK100 */
446 reg = <5>;
Michal Simekfddff682021-03-11 13:34:02 +0100447 always-on;
Michal Simekce906542020-11-26 14:25:02 +0100448 };
449 si5341_6: out@6 {
450 /* refclk6 PL CLK125 */
451 reg = <6>;
Michal Simekfddff682021-03-11 13:34:02 +0100452 always-on;
Michal Simekce906542020-11-26 14:25:02 +0100453 };
454 si5341_9: out@9 {
455 /* refclk9 used for PS_REF_CLK 33.3 MHz */
456 reg = <9>;
Michal Simekfddff682021-03-11 13:34:02 +0100457 always-on;
Michal Simekce906542020-11-26 14:25:02 +0100458 };
459 };
Michal Simeka81186f2019-11-25 08:38:25 +0100460 };
461 i2c_si570_user_c0: i2c@2 {
462 #address-cells = <1>;
463 #size-cells = <0>;
464 reg = <2>;
465 si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
466 #clock-cells = <0>;
467 compatible = "silabs,si570";
468 reg = <0x5d>;
469 temperature-stability = <50>;
470 factory-fout = <300000000>;
471 clock-frequency = <300000000>;
472 clock-output-names = "si570_user_c0";
473 };
474 };
475 i2c_si570_mgt: i2c@3 {
476 #address-cells = <1>;
477 #size-cells = <0>;
478 reg = <3>;
479 si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
480 #clock-cells = <0>;
481 compatible = "silabs,si570";
482 reg = <0x5d>;
483 temperature-stability = <50>;
484 factory-fout = <156250000>;
485 clock-frequency = <148500000>;
486 clock-output-names = "si570_mgt";
487 };
488 };
489 i2c_8a34001: i2c@4 {
490 #address-cells = <1>;
491 #size-cells = <0>;
492 reg = <4>;
Michal Simek9577b2e2021-01-22 14:42:29 +0100493 idt_8a34001: phc@5b {
494 compatible = "idt,8a34001"; /* u409B */
495 reg = <0x5b>;
496 };
Michal Simeka81186f2019-11-25 08:38:25 +0100497 };
498 i2c_clk104: i2c@5 {
499 #address-cells = <1>;
500 #size-cells = <0>;
501 reg = <5>;
502 /* CLK104_SDA */
503 };
504 i2c@6 {
505 #address-cells = <1>;
506 #size-cells = <0>;
507 reg = <6>;
508 /* RFMCP connector */
509 };
510 /* 7 NC */
511 };
512
513 i2c-mux@75 {
514 compatible = "nxp,pca9548"; /* u22 */
515 #address-cells = <1>;
516 #size-cells = <0>;
517 reg = <0x75>;
Raviteja Narayanam486f25c2021-04-01 07:14:10 -0600518 i2c-mux-idle-disconnect;
Michal Simeka81186f2019-11-25 08:38:25 +0100519 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
520 i2c@0 {
521 #address-cells = <1>;
522 #size-cells = <0>;
523 reg = <0>;
524 /* FMCP_HSPC_IIC */
525 };
526 i2c_si570_user_c1: i2c@1 {
527 #address-cells = <1>;
528 #size-cells = <0>;
529 reg = <1>;
530 si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */
531 #clock-cells = <0>;
532 compatible = "silabs,si570";
533 reg = <0x5d>;
534 temperature-stability = <50>;
535 factory-fout = <300000000>;
536 clock-frequency = <300000000>;
537 clock-output-names = "si570_user_c1";
538 };
539 };
540 i2c@2 {
541 #address-cells = <1>;
542 #size-cells = <0>;
543 reg = <2>;
544 /* SYSMON */
545 };
546 i2c@3 {
547 #address-cells = <1>;
548 #size-cells = <0>;
549 reg = <3>;
550 /* DDR4 SODIMM */
551 };
552 i2c@4 {
553 #address-cells = <1>;
554 #size-cells = <0>;
555 reg = <4>;
556 /* SFP3 */
557 };
558 i2c@5 {
559 #address-cells = <1>;
560 #size-cells = <0>;
561 reg = <5>;
562 /* SFP2 */
563 };
564 i2c@6 {
565 #address-cells = <1>;
566 #size-cells = <0>;
567 reg = <6>;
568 /* SFP1 */
569 };
570 i2c@7 {
571 #address-cells = <1>;
572 #size-cells = <0>;
573 reg = <7>;
574 /* SFP0 */
575 };
576 };
577 /* MSP430 */
578};
579
Michal Simekbd008492021-05-10 13:14:02 +0200580&pinctrl0 {
581 status = "okay";
582 pinctrl_i2c0_default: i2c0-default {
583 mux {
584 groups = "i2c0_3_grp";
585 function = "i2c0";
586 };
587
588 conf {
589 groups = "i2c0_3_grp";
590 bias-pull-up;
591 slew-rate = <SLEW_RATE_SLOW>;
592 power-source = <IO_STANDARD_LVCMOS18>;
593 };
594 };
595
596 pinctrl_i2c0_gpio: i2c0-gpio {
597 mux {
598 groups = "gpio0_14_grp", "gpio0_15_grp";
599 function = "gpio0";
600 };
601
602 conf {
603 groups = "gpio0_14_grp", "gpio0_15_grp";
604 slew-rate = <SLEW_RATE_SLOW>;
605 power-source = <IO_STANDARD_LVCMOS18>;
606 };
607 };
608
609 pinctrl_i2c1_default: i2c1-default {
610 mux {
611 groups = "i2c1_4_grp";
612 function = "i2c1";
613 };
614
615 conf {
616 groups = "i2c1_4_grp";
617 bias-pull-up;
618 slew-rate = <SLEW_RATE_SLOW>;
619 power-source = <IO_STANDARD_LVCMOS18>;
620 };
621 };
622
623 pinctrl_i2c1_gpio: i2c1-gpio {
624 mux {
625 groups = "gpio0_16_grp", "gpio0_17_grp";
626 function = "gpio0";
627 };
628
629 conf {
630 groups = "gpio0_16_grp", "gpio0_17_grp";
631 slew-rate = <SLEW_RATE_SLOW>;
632 power-source = <IO_STANDARD_LVCMOS18>;
633 };
634 };
635};
636
Michal Simeka81186f2019-11-25 08:38:25 +0100637&qspi {
638 status = "okay";
639 is-dual = <1>;
640 flash@0 {
641 compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
642 #address-cells = <1>;
643 #size-cells = <1>;
644 reg = <0>;
645 spi-tx-bus-width = <1>;
646 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
647 spi-max-frequency = <108000000>; /* Based on DC1 spec */
648 };
649};
650
Michal Simekce906542020-11-26 14:25:02 +0100651&psgtr {
652 status = "okay";
Michal Simek1242a6b2021-05-31 09:56:58 +0200653 /* nc, nc, usb3, sata */
654 clocks = <&si5341 0 2>, <&si5341 0 3>;
655 clock-names = "ref2", "ref3";
Michal Simekce906542020-11-26 14:25:02 +0100656};
657
Michal Simeka81186f2019-11-25 08:38:25 +0100658&rtc {
659 status = "okay";
660};
661
662&sata {
663 status = "okay";
664 /* SATA OOB timing settings */
665 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
666 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
667 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
668 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
669 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
670 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
671 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
672 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
Michal Simek31958402021-05-10 14:55:34 +0200673 phy-names = "sata-phy";
Michal Simekce906542020-11-26 14:25:02 +0100674 phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
Michal Simeka81186f2019-11-25 08:38:25 +0100675};
676
677/* SD1 with level shifter */
678&sdhci1 {
679 status = "okay";
680 disable-wp;
Manish Narani12ffe752020-02-13 23:37:30 -0700681 /*
682 * This property should be removed for supporting UHS mode
683 */
684 no-1-8-v;
Michal Simek01a6da12020-07-22 17:42:43 +0200685 xlnx,mio-bank = <1>;
Michal Simeka81186f2019-11-25 08:38:25 +0100686};
687
Michal Simeka81186f2019-11-25 08:38:25 +0100688&uart0 {
689 status = "okay";
690};
691
692/* ULPI SMSC USB3320 */
693&usb0 {
694 status = "okay";
Manish Narani15ca9eb2021-07-14 06:17:19 -0600695 phy-names = "usb3-phy";
696 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
Michal Simeka81186f2019-11-25 08:38:25 +0100697};
698
699&dwc3_0 {
700 status = "okay";
701 dr_mode = "host";
702 snps,usb3_lpm_capable;
Michal Simek184309b2021-05-31 17:51:58 +0200703 maximum-speed = "super-speed";
Michal Simeka81186f2019-11-25 08:38:25 +0100704};