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Anton Vorontsov42dbd662008-05-28 18:20:15 +04001/*
2 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13#ifndef __ASM_PPC_FSL_LBC_H
14#define __ASM_PPC_FSL_LBC_H
15
16#include <config.h>
17
18/* BR - Base Registers
19 */
20#define BR0 0x5000 /* Register offset to immr */
21#define BR1 0x5008
22#define BR2 0x5010
23#define BR3 0x5018
24#define BR4 0x5020
25#define BR5 0x5028
26#define BR6 0x5030
27#define BR7 0x5038
28
29#define BR_BA 0xFFFF8000
30#define BR_BA_SHIFT 15
31#define BR_PS 0x00001800
32#define BR_PS_SHIFT 11
33#define BR_PS_8 0x00000800 /* Port Size 8 bit */
34#define BR_PS_16 0x00001000 /* Port Size 16 bit */
35#define BR_PS_32 0x00001800 /* Port Size 32 bit */
36#define BR_DECC 0x00000600
37#define BR_DECC_SHIFT 9
38#define BR_DECC_OFF 0x00000000
39#define BR_DECC_CHK 0x00000200
40#define BR_DECC_CHK_GEN 0x00000400
41#define BR_WP 0x00000100
42#define BR_WP_SHIFT 8
43#define BR_MSEL 0x000000E0
44#define BR_MSEL_SHIFT 5
45#define BR_MS_GPCM 0x00000000 /* GPCM */
46#define BR_MS_FCM 0x00000020 /* FCM */
Anton Vorontsovc8c5fc22008-05-29 18:14:56 +040047#ifdef CONFIG_MPC83xx
Anton Vorontsov42dbd662008-05-28 18:20:15 +040048#define BR_MS_SDRAM 0x00000060 /* SDRAM */
Anton Vorontsovc8c5fc22008-05-29 18:14:56 +040049#elif defined(CONFIG_MPC85xx)
50#define BR_MS_SDRAM 0x00000000 /* SDRAM */
51#endif
Anton Vorontsov42dbd662008-05-28 18:20:15 +040052#define BR_MS_UPMA 0x00000080 /* UPMA */
53#define BR_MS_UPMB 0x000000A0 /* UPMB */
54#define BR_MS_UPMC 0x000000C0 /* UPMC */
55#if !defined(CONFIG_MPC834X)
56#define BR_ATOM 0x0000000C
57#define BR_ATOM_SHIFT 2
58#endif
59#define BR_V 0x00000001
60#define BR_V_SHIFT 0
61
62#if defined(CONFIG_MPC834X)
63#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
64#else
65#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
66#endif
67
68/* OR - Option Registers
69 */
70#define OR0 0x5004 /* Register offset to immr */
71#define OR1 0x500C
72#define OR2 0x5014
73#define OR3 0x501C
74#define OR4 0x5024
75#define OR5 0x502C
76#define OR6 0x5034
77#define OR7 0x503C
78
79#define OR_GPCM_AM 0xFFFF8000
80#define OR_GPCM_AM_SHIFT 15
81#define OR_GPCM_BCTLD 0x00001000
82#define OR_GPCM_BCTLD_SHIFT 12
83#define OR_GPCM_CSNT 0x00000800
84#define OR_GPCM_CSNT_SHIFT 11
85#define OR_GPCM_ACS 0x00000600
86#define OR_GPCM_ACS_SHIFT 9
Anton Vorontsovc8c5fc22008-05-29 18:14:56 +040087#define OR_GPCM_ACS_DIV2 0x00000600
88#define OR_GPCM_ACS_DIV4 0x00000400
Anton Vorontsov42dbd662008-05-28 18:20:15 +040089#define OR_GPCM_XACS 0x00000100
90#define OR_GPCM_XACS_SHIFT 8
91#define OR_GPCM_SCY 0x000000F0
92#define OR_GPCM_SCY_SHIFT 4
93#define OR_GPCM_SCY_1 0x00000010
94#define OR_GPCM_SCY_2 0x00000020
95#define OR_GPCM_SCY_3 0x00000030
96#define OR_GPCM_SCY_4 0x00000040
97#define OR_GPCM_SCY_5 0x00000050
98#define OR_GPCM_SCY_6 0x00000060
99#define OR_GPCM_SCY_7 0x00000070
100#define OR_GPCM_SCY_8 0x00000080
101#define OR_GPCM_SCY_9 0x00000090
102#define OR_GPCM_SCY_10 0x000000a0
103#define OR_GPCM_SCY_11 0x000000b0
104#define OR_GPCM_SCY_12 0x000000c0
105#define OR_GPCM_SCY_13 0x000000d0
106#define OR_GPCM_SCY_14 0x000000e0
107#define OR_GPCM_SCY_15 0x000000f0
108#define OR_GPCM_SETA 0x00000008
109#define OR_GPCM_SETA_SHIFT 3
110#define OR_GPCM_TRLX 0x00000004
111#define OR_GPCM_TRLX_SHIFT 2
112#define OR_GPCM_EHTR 0x00000002
113#define OR_GPCM_EHTR_SHIFT 1
114#define OR_GPCM_EAD 0x00000001
115#define OR_GPCM_EAD_SHIFT 0
116
Anton Vorontsovc8c5fc22008-05-29 18:14:56 +0400117/* helpers to convert values into an OR address mask (GPCM mode) */
118#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
119#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
120
Anton Vorontsov42dbd662008-05-28 18:20:15 +0400121#define OR_FCM_AM 0xFFFF8000
122#define OR_FCM_AM_SHIFT 15
123#define OR_FCM_BCTLD 0x00001000
124#define OR_FCM_BCTLD_SHIFT 12
125#define OR_FCM_PGS 0x00000400
126#define OR_FCM_PGS_SHIFT 10
127#define OR_FCM_CSCT 0x00000200
128#define OR_FCM_CSCT_SHIFT 9
129#define OR_FCM_CST 0x00000100
130#define OR_FCM_CST_SHIFT 8
131#define OR_FCM_CHT 0x00000080
132#define OR_FCM_CHT_SHIFT 7
133#define OR_FCM_SCY 0x00000070
134#define OR_FCM_SCY_SHIFT 4
135#define OR_FCM_SCY_1 0x00000010
136#define OR_FCM_SCY_2 0x00000020
137#define OR_FCM_SCY_3 0x00000030
138#define OR_FCM_SCY_4 0x00000040
139#define OR_FCM_SCY_5 0x00000050
140#define OR_FCM_SCY_6 0x00000060
141#define OR_FCM_SCY_7 0x00000070
142#define OR_FCM_RST 0x00000008
143#define OR_FCM_RST_SHIFT 3
144#define OR_FCM_TRLX 0x00000004
145#define OR_FCM_TRLX_SHIFT 2
146#define OR_FCM_EHTR 0x00000002
147#define OR_FCM_EHTR_SHIFT 1
148
149#define OR_UPM_AM 0xFFFF8000
150#define OR_UPM_AM_SHIFT 15
151#define OR_UPM_XAM 0x00006000
152#define OR_UPM_XAM_SHIFT 13
153#define OR_UPM_BCTLD 0x00001000
154#define OR_UPM_BCTLD_SHIFT 12
155#define OR_UPM_BI 0x00000100
156#define OR_UPM_BI_SHIFT 8
157#define OR_UPM_TRLX 0x00000004
158#define OR_UPM_TRLX_SHIFT 2
159#define OR_UPM_EHTR 0x00000002
160#define OR_UPM_EHTR_SHIFT 1
161#define OR_UPM_EAD 0x00000001
162#define OR_UPM_EAD_SHIFT 0
163
Anton Vorontsovc8c5fc22008-05-29 18:14:56 +0400164#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
165#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
166#define MxMR_OP_WARR 0x10000000 /* Write to Array */
167#define MxMR_BSEL 0x80000000 /* Bus Select */
168
Anton Vorontsov42dbd662008-05-28 18:20:15 +0400169#define OR_SDRAM_AM 0xFFFF8000
170#define OR_SDRAM_AM_SHIFT 15
171#define OR_SDRAM_XAM 0x00006000
172#define OR_SDRAM_XAM_SHIFT 13
173#define OR_SDRAM_COLS 0x00001C00
174#define OR_SDRAM_COLS_SHIFT 10
175#define OR_SDRAM_ROWS 0x000001C0
176#define OR_SDRAM_ROWS_SHIFT 6
177#define OR_SDRAM_PMSEL 0x00000020
178#define OR_SDRAM_PMSEL_SHIFT 5
179#define OR_SDRAM_EAD 0x00000001
180#define OR_SDRAM_EAD_SHIFT 0
181
182#define OR_AM_32KB 0xFFFF8000
183#define OR_AM_64KB 0xFFFF0000
184#define OR_AM_128KB 0xFFFE0000
185#define OR_AM_256KB 0xFFFC0000
186#define OR_AM_512KB 0xFFF80000
187#define OR_AM_1MB 0xFFF00000
188#define OR_AM_2MB 0xFFE00000
189#define OR_AM_4MB 0xFFC00000
190#define OR_AM_8MB 0xFF800000
191#define OR_AM_16MB 0xFF000000
192#define OR_AM_32MB 0xFE000000
193#define OR_AM_64MB 0xFC000000
194#define OR_AM_128MB 0xF8000000
195#define OR_AM_256MB 0xF0000000
196#define OR_AM_512MB 0xE0000000
197#define OR_AM_1GB 0xC0000000
198#define OR_AM_2GB 0x80000000
199#define OR_AM_4GB 0x00000000
200
201#define LBLAWAR_EN 0x80000000
202#define LBLAWAR_4KB 0x0000000B
203#define LBLAWAR_8KB 0x0000000C
204#define LBLAWAR_16KB 0x0000000D
205#define LBLAWAR_32KB 0x0000000E
206#define LBLAWAR_64KB 0x0000000F
207#define LBLAWAR_128KB 0x00000010
208#define LBLAWAR_256KB 0x00000011
209#define LBLAWAR_512KB 0x00000012
210#define LBLAWAR_1MB 0x00000013
211#define LBLAWAR_2MB 0x00000014
212#define LBLAWAR_4MB 0x00000015
213#define LBLAWAR_8MB 0x00000016
214#define LBLAWAR_16MB 0x00000017
215#define LBLAWAR_32MB 0x00000018
216#define LBLAWAR_64MB 0x00000019
217#define LBLAWAR_128MB 0x0000001A
218#define LBLAWAR_256MB 0x0000001B
219#define LBLAWAR_512MB 0x0000001C
220#define LBLAWAR_1GB 0x0000001D
221#define LBLAWAR_2GB 0x0000001E
222
223/* LBCR - Local Bus Configuration Register
224 */
225#define LBCR_LDIS 0x80000000
226#define LBCR_LDIS_SHIFT 31
227#define LBCR_BCTLC 0x00C00000
228#define LBCR_BCTLC_SHIFT 22
229#define LBCR_LPBSE 0x00020000
230#define LBCR_LPBSE_SHIFT 17
231#define LBCR_EPAR 0x00010000
232#define LBCR_EPAR_SHIFT 16
233#define LBCR_BMT 0x0000FF00
234#define LBCR_BMT_SHIFT 8
235
236/* LCRR - Clock Ratio Register
237 */
238#define LCRR_DBYP 0x80000000
239#define LCRR_DBYP_SHIFT 31
240#define LCRR_BUFCMDC 0x30000000
241#define LCRR_BUFCMDC_SHIFT 28
242#define LCRR_BUFCMDC_1 0x10000000
243#define LCRR_BUFCMDC_2 0x20000000
244#define LCRR_BUFCMDC_3 0x30000000
245#define LCRR_BUFCMDC_4 0x00000000
246#define LCRR_ECL 0x03000000
247#define LCRR_ECL_SHIFT 24
248#define LCRR_ECL_4 0x00000000
249#define LCRR_ECL_5 0x01000000
250#define LCRR_ECL_6 0x02000000
251#define LCRR_ECL_7 0x03000000
252#define LCRR_EADC 0x00030000
253#define LCRR_EADC_SHIFT 16
254#define LCRR_EADC_1 0x00010000
255#define LCRR_EADC_2 0x00020000
256#define LCRR_EADC_3 0x00030000
257#define LCRR_EADC_4 0x00000000
258#define LCRR_CLKDIV 0x0000000F
259#define LCRR_CLKDIV_SHIFT 0
260#define LCRR_CLKDIV_2 0x00000002
261#define LCRR_CLKDIV_4 0x00000004
262#define LCRR_CLKDIV_8 0x00000008
263
264#endif /* __ASM_PPC_FSL_LBC_H */