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Masahiro Yamadadd840582014-07-30 14:08:14 +09001menu "MIPS architecture"
2 depends on MIPS
3
4config SYS_ARCH
Masahiro Yamadadd840582014-07-30 14:08:14 +09005 default "mips"
6
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +01007config SYS_CPU
Paul Burton20286cd2016-05-16 10:52:11 +01008 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +010010
Masahiro Yamadadd840582014-07-30 14:08:14 +090011choice
12 prompt "Target select"
Joe Hershbergera26cd042015-05-12 14:46:23 -050013 optional
Masahiro Yamadadd840582014-07-30 14:08:14 +090014
15config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
Michal Simek5ed063d2018-07-23 15:55:13 +020017 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010018 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010019 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
Daniel Schwierzeckaa45f752014-10-26 14:14:07 +010021 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
Michal Simek5ed063d2018-07-23 15:55:13 +020023 select SUPPORTS_LITTLE_ENDIAN
Masahiro Yamadadd840582014-07-30 14:08:14 +090024
25config TARGET_MALTA
26 bool "Support malta"
Paul Burton6242aa12016-05-17 07:43:28 +010027 select DM
28 select DM_SERIAL
Paul Burton05e34252016-01-29 13:54:52 +000029 select DYNAMIC_IO_PORT_BASE
Paul Burton566ce04d2016-09-21 11:18:56 +010030 select MIPS_CM
Daniel Schwierzeckd1c3d8b2018-09-07 19:18:44 +020031 select MIPS_INSERT_BOOT_CONFIG
Michal Simek5ed063d2018-07-23 15:55:13 +020032 select MIPS_L1_CACHE_SHIFT_6
Paul Burton566ce04d2016-09-21 11:18:56 +010033 select MIPS_L2_CACHE
Paul Burton6242aa12016-05-17 07:43:28 +010034 select OF_CONTROL
35 select OF_ISA_BUS
Michal Simek5ed063d2018-07-23 15:55:13 +020036 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010037 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010038 select SUPPORTS_CPU_MIPS32_R1
39 select SUPPORTS_CPU_MIPS32_R2
Paul Burton40ba13c2016-05-16 10:52:14 +010040 select SUPPORTS_CPU_MIPS32_R6
Paul Burton0f832b92016-05-26 14:49:36 +010041 select SUPPORTS_CPU_MIPS64_R1
42 select SUPPORTS_CPU_MIPS64_R2
43 select SUPPORTS_CPU_MIPS64_R6
Michal Simek5ed063d2018-07-23 15:55:13 +020044 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +010045 select SWAP_IO_SPACE
Michal Simek08a00cb2018-07-23 15:55:14 +020046 imply CMD_DM
Masahiro Yamadadd840582014-07-30 14:08:14 +090047
48config TARGET_VCT
49 bool "Support vct"
Michal Simek5ed063d2018-07-23 15:55:13 +020050 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010051 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010052 select SUPPORTS_CPU_MIPS32_R1
53 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +000054 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Masahiro Yamadadd840582014-07-30 14:08:14 +090055
Wills Wang1d3d0f12016-03-16 16:59:52 +080056config ARCH_ATH79
57 bool "Support QCA/Atheros ath79"
Wills Wang1d3d0f12016-03-16 16:59:52 +080058 select DM
Michal Simek5ed063d2018-07-23 15:55:13 +020059 select OF_CONTROL
Michal Simek08a00cb2018-07-23 15:55:14 +020060 imply CMD_DM
Wills Wang1d3d0f12016-03-16 16:59:52 +080061
Gregory CLEMENTdd1033e2018-12-14 16:16:47 +010062config ARCH_MSCC
63 bool "Support MSCC VCore-III"
64 select OF_CONTROL
65 select DM
66
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +020067config ARCH_BMIPS
68 bool "Support BMIPS SoCs"
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +020069 select CLK
70 select CPU
Michal Simek5ed063d2018-07-23 15:55:13 +020071 select DM
72 select OF_CONTROL
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +020073 select RAM
74 select SYSRESET
Michal Simek08a00cb2018-07-23 15:55:14 +020075 imply CMD_DM
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +020076
Stefan Roese4c835a62018-09-05 15:12:35 +020077config ARCH_MT7620
78 bool "Support MT7620/7688 SoCs"
79 imply CMD_DM
80 select DISPLAY_CPUINFO
81 select DM
Stefan Roeseb4a6a1b2018-10-09 08:59:09 +020082 imply DM_ETH
83 imply DM_GPIO
Stefan Roese4c835a62018-09-05 15:12:35 +020084 select DM_SERIAL
85 imply DM_SPI
86 imply DM_SPI_FLASH
Stefan Roesea5f50e02018-12-18 10:27:14 +010087 select ARCH_MISC_INIT
Stefan Roese4c835a62018-09-05 15:12:35 +020088 select MIPS_TUNE_24KC
89 select OF_CONTROL
90 select ROM_EXCEPTION_VECTORS
91 select SUPPORTS_CPU_MIPS32_R1
92 select SUPPORTS_CPU_MIPS32_R2
93 select SUPPORTS_LITTLE_ENDIAN
Stefan Roese41f6e6e2018-08-16 15:27:32 +020094 select SYSRESET
Stefan Roese4c835a62018-09-05 15:12:35 +020095
Paul Burtoncd71b1d2018-12-16 19:25:22 -030096config ARCH_JZ47XX
97 bool "Support Ingenic JZ47xx"
98 select SUPPORT_SPL
99 select OF_CONTROL
100 select DM
101
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530102config MACH_PIC32
103 bool "Support Microchip PIC32"
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530104 select DM
Michal Simek5ed063d2018-07-23 15:55:13 +0200105 select OF_CONTROL
Michal Simek08a00cb2018-07-23 15:55:14 +0200106 imply CMD_DM
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530107
Paul Burtonad8783c2016-09-08 07:47:39 +0100108config TARGET_BOSTON
109 bool "Support Boston"
110 select DM
111 select DM_SERIAL
Paul Burtonad8783c2016-09-08 07:47:39 +0100112 select MIPS_CM
113 select MIPS_L1_CACHE_SHIFT_6
114 select MIPS_L2_CACHE
Paul Burtond2b12a52017-04-30 21:22:42 +0200115 select OF_BOARD_SETUP
Michal Simek5ed063d2018-07-23 15:55:13 +0200116 select OF_CONTROL
117 select ROM_EXCEPTION_VECTORS
Paul Burtonad8783c2016-09-08 07:47:39 +0100118 select SUPPORTS_BIG_ENDIAN
Paul Burtonad8783c2016-09-08 07:47:39 +0100119 select SUPPORTS_CPU_MIPS32_R1
120 select SUPPORTS_CPU_MIPS32_R2
121 select SUPPORTS_CPU_MIPS32_R6
122 select SUPPORTS_CPU_MIPS64_R1
123 select SUPPORTS_CPU_MIPS64_R2
124 select SUPPORTS_CPU_MIPS64_R6
Michal Simek5ed063d2018-07-23 15:55:13 +0200125 select SUPPORTS_LITTLE_ENDIAN
Michal Simek08a00cb2018-07-23 15:55:14 +0200126 imply CMD_DM
Paul Burtonad8783c2016-09-08 07:47:39 +0100127
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100128config TARGET_XILFPGA
129 bool "Support Imagination Xilfpga"
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100130 select DM
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100131 select DM_ETH
Michal Simek5ed063d2018-07-23 15:55:13 +0200132 select DM_GPIO
133 select DM_SERIAL
134 select MIPS_L1_CACHE_SHIFT_4
135 select OF_CONTROL
136 select ROM_EXCEPTION_VECTORS
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100137 select SUPPORTS_CPU_MIPS32_R1
138 select SUPPORTS_CPU_MIPS32_R2
Michal Simek5ed063d2018-07-23 15:55:13 +0200139 select SUPPORTS_LITTLE_ENDIAN
Michal Simek08a00cb2018-07-23 15:55:14 +0200140 imply CMD_DM
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100141 help
142 This supports IMGTEC MIPSfpga platform
143
Masahiro Yamadadd840582014-07-30 14:08:14 +0900144endchoice
145
Paul Burtonad8783c2016-09-08 07:47:39 +0100146source "board/imgtec/boston/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900147source "board/imgtec/malta/Kconfig"
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100148source "board/imgtec/xilfpga/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900149source "board/micronas/vct/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900150source "board/qemu-mips/Kconfig"
Wills Wang1d3d0f12016-03-16 16:59:52 +0800151source "arch/mips/mach-ath79/Kconfig"
Gregory CLEMENTdd1033e2018-12-14 16:16:47 +0100152source "arch/mips/mach-mscc/Kconfig"
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +0200153source "arch/mips/mach-bmips/Kconfig"
Paul Burtoncd71b1d2018-12-16 19:25:22 -0300154source "arch/mips/mach-jz47xx/Kconfig"
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530155source "arch/mips/mach-pic32/Kconfig"
Stefan Roese4c835a62018-09-05 15:12:35 +0200156source "arch/mips/mach-mt7620/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900157
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100158if MIPS
159
160choice
161 prompt "Endianness selection"
162 help
163 Some MIPS boards can be configured for either little or big endian
164 byte order. These modes require different U-Boot images. In general there
165 is one preferred byteorder for a particular system but some systems are
166 just as commonly used in the one or the other endianness.
167
168config SYS_BIG_ENDIAN
169 bool "Big endian"
170 depends on SUPPORTS_BIG_ENDIAN
171
172config SYS_LITTLE_ENDIAN
173 bool "Little endian"
174 depends on SUPPORTS_LITTLE_ENDIAN
175
176endchoice
177
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100178choice
179 prompt "CPU selection"
180 default CPU_MIPS32_R2
181
182config CPU_MIPS32_R1
183 bool "MIPS32 Release 1"
184 depends on SUPPORTS_CPU_MIPS32_R1
185 select 32BIT
186 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100187 Choose this option to build an U-Boot for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100188 MIPS32 architecture.
189
190config CPU_MIPS32_R2
191 bool "MIPS32 Release 2"
192 depends on SUPPORTS_CPU_MIPS32_R2
193 select 32BIT
194 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100195 Choose this option to build an U-Boot for release 2 through 5 of the
196 MIPS32 architecture.
197
198config CPU_MIPS32_R6
199 bool "MIPS32 Release 6"
200 depends on SUPPORTS_CPU_MIPS32_R6
201 select 32BIT
202 help
203 Choose this option to build an U-Boot for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100204 MIPS32 architecture.
205
206config CPU_MIPS64_R1
207 bool "MIPS64 Release 1"
208 depends on SUPPORTS_CPU_MIPS64_R1
209 select 64BIT
210 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100211 Choose this option to build a kernel for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100212 MIPS64 architecture.
213
214config CPU_MIPS64_R2
215 bool "MIPS64 Release 2"
216 depends on SUPPORTS_CPU_MIPS64_R2
217 select 64BIT
218 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100219 Choose this option to build a kernel for release 2 through 5 of the
220 MIPS64 architecture.
221
222config CPU_MIPS64_R6
223 bool "MIPS64 Release 6"
224 depends on SUPPORTS_CPU_MIPS64_R6
225 select 64BIT
226 help
227 Choose this option to build a kernel for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100228 MIPS64 architecture.
229
230endchoice
231
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +0100232menu "General setup"
233
234config ROM_EXCEPTION_VECTORS
235 bool "Build U-Boot image with exception vectors"
236 help
237 Enable this to include exception vectors in the U-Boot image. This is
238 required if the U-Boot entry point is equal to the address of the
239 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
240 U-Boot booted from parallel NOR flash).
241 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
242 In that case the image size will be reduced by 0x500 bytes.
243
Paul Burton939a2552017-05-12 13:26:11 +0200244config MIPS_CM_BASE
245 hex "MIPS CM GCR Base Address"
246 depends on MIPS_CM
Paul Burtoned048e72017-04-30 21:22:41 +0200247 default 0x16100000 if TARGET_BOSTON
Paul Burton939a2552017-05-12 13:26:11 +0200248 default 0x1fbf8000
249 help
250 The physical base address at which to map the MIPS Coherence Manager
251 Global Configuration Registers (GCRs). This should be set such that
252 the GCRs occupy a region of the physical address space which is
253 otherwise unused, or at minimum that software doesn't need to access.
254
Daniel Schwierzeck5ef337a2018-09-07 19:02:05 +0200255config MIPS_CACHE_INDEX_BASE
256 hex "Index base address for cache initialisation"
257 default 0x80000000 if CPU_MIPS32
258 default 0xffffffff80000000 if CPU_MIPS64
259 help
260 This is the base address for a memory block, which is used for
261 initialising the cache lines. This is also the base address of a memory
262 block which is used for loading and filling cache lines when
263 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
264 Normally this is CKSEG0. If the MIPS system needs to move this block
265 to some SRAM or ScratchPad RAM, adapt this option accordingly.
266
Daniel Schwierzeck96301462018-11-01 02:02:21 +0100267config MIPS_RELOCATION_TABLE_SIZE
268 hex "Relocation table size"
269 range 0x100 0x10000
270 default "0x8000"
271 ---help---
272 A table of relocation data will be appended to the U-Boot binary
273 and parsed in relocate_code() to fix up all offsets in the relocated
274 U-Boot.
275
276 This option allows the amount of space reserved for the table to be
277 adjusted in a range from 256 up to 64k. The default is 32k and should
278 be ok in most cases. Reduce this value to shrink the size of U-Boot
279 binary.
280
281 The build will fail and a valid size suggested if this is too small.
282
283 If unsure, leave at the default value.
284
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +0100285endmenu
286
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100287menu "OS boot interface"
288
289config MIPS_BOOT_CMDLINE_LEGACY
290 bool "Hand over legacy command line to Linux kernel"
291 default y
292 help
293 Enable this option if you want U-Boot to hand over the Yamon-style
294 command line to the kernel. All bootargs will be prepared as argc/argv
295 compatible list. The argument count (argc) is stored in register $a0.
296 The address of the argument list (argv) is stored in register $a1.
297
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100298config MIPS_BOOT_ENV_LEGACY
299 bool "Hand over legacy environment to Linux kernel"
300 default y
301 help
302 Enable this option if you want U-Boot to hand over the Yamon-style
303 environment to the kernel. Information like memory size, initrd
304 address and size will be prepared as zero-terminated key/value list.
Robert P. J. Day1cc0a9f2016-05-04 04:47:31 -0400305 The address of the environment is stored in register $a2.
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100306
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100307config MIPS_BOOT_FDT
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100308 bool "Hand over a flattened device tree to Linux kernel"
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100309 default n
310 help
311 Enable this option if you want U-Boot to hand over a flattened
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100312 device tree to the kernel. According to UHI register $a0 will be set
313 to -2 and the FDT address is stored in $a1.
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100314
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100315endmenu
316
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100317config SUPPORTS_BIG_ENDIAN
318 bool
319
320config SUPPORTS_LITTLE_ENDIAN
321 bool
322
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100323config SUPPORTS_CPU_MIPS32_R1
324 bool
325
326config SUPPORTS_CPU_MIPS32_R2
327 bool
328
Paul Burtonc52ebea2016-05-16 10:52:12 +0100329config SUPPORTS_CPU_MIPS32_R6
330 bool
331
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100332config SUPPORTS_CPU_MIPS64_R1
333 bool
334
335config SUPPORTS_CPU_MIPS64_R2
336 bool
337
Paul Burtonc52ebea2016-05-16 10:52:12 +0100338config SUPPORTS_CPU_MIPS64_R6
339 bool
340
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100341config CPU_MIPS32
342 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100343 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100344
345config CPU_MIPS64
346 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100347 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100348
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100349config MIPS_TUNE_4KC
350 bool
351
352config MIPS_TUNE_14KC
353 bool
354
355config MIPS_TUNE_24KC
356 bool
357
Daniel Schwierzeck5f9cc362016-05-27 15:39:39 +0200358config MIPS_TUNE_34KC
359 bool
360
Marek Vasut0a0a9582016-05-06 20:10:33 +0200361config MIPS_TUNE_74KC
362 bool
363
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100364config 32BIT
365 bool
366
367config 64BIT
368 bool
369
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +0100370config SWAP_IO_SPACE
371 bool
372
Paul Burtondd7c7202015-01-29 01:28:02 +0000373config SYS_MIPS_CACHE_INIT_RAM_LOAD
374 bool
375
Daniel Schwierzeck924ad862016-06-04 16:13:21 +0200376config MIPS_INIT_STACK_IN_SRAM
377 bool
378 default n
379 help
380 Select this if the initial stack frame could be setup in SRAM.
381 Normally the initial stack frame is set up in DRAM which is often
382 only available after lowlevel_init. With this option the initial
383 stack frame and the early C environment is set up before
384 lowlevel_init. Thus lowlevel_init does not need to be implemented
385 in assembler.
386
Paul Burtonace3be42016-05-27 14:28:04 +0100387config SYS_DCACHE_SIZE
388 int
389 default 0
390 help
391 The total size of the L1 Dcache, if known at compile time.
392
Paul Burton37228622016-05-27 14:28:05 +0100393config SYS_DCACHE_LINE_SIZE
Paul Burton4b7b0a02016-06-09 13:09:52 +0100394 int
Paul Burton37228622016-05-27 14:28:05 +0100395 default 0
396 help
397 The size of L1 Dcache lines, if known at compile time.
398
Paul Burtonace3be42016-05-27 14:28:04 +0100399config SYS_ICACHE_SIZE
400 int
401 default 0
402 help
403 The total size of the L1 ICache, if known at compile time.
404
Paul Burton37228622016-05-27 14:28:05 +0100405config SYS_ICACHE_LINE_SIZE
Paul Burtonace3be42016-05-27 14:28:04 +0100406 int
407 default 0
408 help
Paul Burton37228622016-05-27 14:28:05 +0100409 The size of L1 Icache lines, if known at compile time.
Paul Burtonace3be42016-05-27 14:28:04 +0100410
411config SYS_CACHE_SIZE_AUTO
412 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
Paul Burton37228622016-05-27 14:28:05 +0100413 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
Paul Burtonace3be42016-05-27 14:28:04 +0100414 help
415 Select this (or let it be auto-selected by not defining any cache
416 sizes) in order to allow U-Boot to automatically detect the sizes
417 of caches at runtime. This has a small cost in code size & runtime
418 so if you know the cache configuration for your system at compile
419 time it would be beneficial to configure it.
420
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +0100421config MIPS_L1_CACHE_SHIFT_4
422 bool
423
424config MIPS_L1_CACHE_SHIFT_5
425 bool
426
427config MIPS_L1_CACHE_SHIFT_6
428 bool
429
430config MIPS_L1_CACHE_SHIFT_7
431 bool
432
433config MIPS_L1_CACHE_SHIFT
434 int
435 default "7" if MIPS_L1_CACHE_SHIFT_7
436 default "6" if MIPS_L1_CACHE_SHIFT_6
437 default "5" if MIPS_L1_CACHE_SHIFT_5
438 default "4" if MIPS_L1_CACHE_SHIFT_4
439 default "5"
440
Paul Burton4baa0ab2016-09-21 11:18:54 +0100441config MIPS_L2_CACHE
442 bool
443 help
444 Select this if your system includes an L2 cache and you want U-Boot
445 to initialise & maintain it.
446
Paul Burton05e34252016-01-29 13:54:52 +0000447config DYNAMIC_IO_PORT_BASE
448 bool
449
Paul Burtonb2b135d2016-09-21 11:18:53 +0100450config MIPS_CM
451 bool
452 help
453 Select this if your system contains a MIPS Coherence Manager and you
454 wish U-Boot to configure it or make use of it to retrieve system
455 information such as cache configuration.
456
Daniel Schwierzeckd1c3d8b2018-09-07 19:18:44 +0200457config MIPS_INSERT_BOOT_CONFIG
458 bool
459 default n
460 help
461 Enable this to insert some board-specific boot configuration in
462 the U-Boot binary at offset 0x10.
463
464config MIPS_BOOT_CONFIG_WORD0
465 hex
466 depends on MIPS_INSERT_BOOT_CONFIG
467 default 0x420 if TARGET_MALTA
468 default 0x0
469 help
470 Value which is inserted as boot config word 0.
471
472config MIPS_BOOT_CONFIG_WORD1
473 hex
474 depends on MIPS_INSERT_BOOT_CONFIG
475 default 0x0
476 help
477 Value which is inserted as boot config word 1.
478
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100479endif
480
Masahiro Yamadadd840582014-07-30 14:08:14 +0900481endmenu