Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000-2002 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <mpc8xx.h> |
| 10 | #include <mpc8xx_irq.h> |
| 11 | #include <asm/processor.h> |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 12 | #include <asm/io.h> |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 13 | #include <commproc.h> |
| 14 | |
| 15 | /************************************************************************/ |
| 16 | |
| 17 | /* |
| 18 | * CPM interrupt vector functions. |
| 19 | */ |
| 20 | struct interrupt_action { |
| 21 | interrupt_handler_t *handler; |
| 22 | void *arg; |
| 23 | }; |
| 24 | |
| 25 | static struct interrupt_action cpm_vecs[CPMVEC_NR]; |
| 26 | static struct interrupt_action irq_vecs[NR_IRQS]; |
| 27 | |
| 28 | static void cpm_interrupt_init (void); |
| 29 | static void cpm_interrupt (void *regs); |
| 30 | |
| 31 | /************************************************************************/ |
| 32 | |
| 33 | int interrupt_init_cpu (unsigned *decrementer_count) |
| 34 | { |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 35 | immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 36 | |
| 37 | *decrementer_count = get_tbclk () / CONFIG_SYS_HZ; |
| 38 | |
| 39 | /* disable all interrupts */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 40 | out_be32(&immr->im_siu_conf.sc_simask, 0); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 41 | |
| 42 | /* Configure CPM interrupts */ |
| 43 | cpm_interrupt_init (); |
| 44 | |
| 45 | return (0); |
| 46 | } |
| 47 | |
| 48 | /************************************************************************/ |
| 49 | |
| 50 | /* |
| 51 | * Handle external interrupts |
| 52 | */ |
| 53 | void external_interrupt (struct pt_regs *regs) |
| 54 | { |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 55 | immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 56 | int irq; |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 57 | ulong simask; |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 58 | ulong vec, v_bit; |
| 59 | |
| 60 | /* |
| 61 | * read the SIVEC register and shift the bits down |
| 62 | * to get the irq number |
| 63 | */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 64 | vec = in_be32(&immr->im_siu_conf.sc_sivec); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 65 | irq = vec >> 26; |
| 66 | v_bit = 0x80000000UL >> irq; |
| 67 | |
| 68 | /* |
| 69 | * Read Interrupt Mask Register and Mask Interrupts |
| 70 | */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 71 | simask = in_be32(&immr->im_siu_conf.sc_simask); |
| 72 | clrbits_be32(&immr->im_siu_conf.sc_simask, 0xFFFF0000 >> irq); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 73 | |
| 74 | if (!(irq & 0x1)) { /* External Interrupt ? */ |
| 75 | ulong siel; |
| 76 | |
| 77 | /* |
| 78 | * Read Interrupt Edge/Level Register |
| 79 | */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 80 | siel = in_be32(&immr->im_siu_conf.sc_siel); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 81 | |
| 82 | if (siel & v_bit) { /* edge triggered interrupt ? */ |
| 83 | /* |
| 84 | * Rewrite SIPEND Register to clear interrupt |
| 85 | */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 86 | out_be32(&immr->im_siu_conf.sc_sipend, v_bit); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 87 | } |
| 88 | } |
| 89 | |
| 90 | if (irq_vecs[irq].handler != NULL) { |
| 91 | irq_vecs[irq].handler (irq_vecs[irq].arg); |
| 92 | } else { |
| 93 | printf ("\nBogus External Interrupt IRQ %d Vector %ld\n", |
| 94 | irq, vec); |
| 95 | /* turn off the bogus interrupt to avoid it from now */ |
| 96 | simask &= ~v_bit; |
| 97 | } |
| 98 | /* |
| 99 | * Re-Enable old Interrupt Mask |
| 100 | */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 101 | out_be32(&immr->im_siu_conf.sc_simask, simask); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | /************************************************************************/ |
| 105 | |
| 106 | /* |
| 107 | * CPM interrupt handler |
| 108 | */ |
| 109 | static void cpm_interrupt (void *regs) |
| 110 | { |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 111 | immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 112 | uint vec; |
| 113 | |
| 114 | /* |
| 115 | * Get the vector by setting the ACK bit |
| 116 | * and then reading the register. |
| 117 | */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 118 | out_be16(&immr->im_cpic.cpic_civr, 1); |
| 119 | vec = in_be16(&immr->im_cpic.cpic_civr); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 120 | vec >>= 11; |
| 121 | |
| 122 | if (cpm_vecs[vec].handler != NULL) { |
| 123 | (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg); |
| 124 | } else { |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 125 | clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 126 | printf ("Masking bogus CPM interrupt vector 0x%x\n", vec); |
| 127 | } |
| 128 | /* |
| 129 | * After servicing the interrupt, |
| 130 | * we have to remove the status indicator. |
| 131 | */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 132 | setbits_be32(&immr->im_cpic.cpic_cisr, 1 << vec); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 133 | } |
| 134 | |
| 135 | /* |
| 136 | * The CPM can generate the error interrupt when there is a race |
| 137 | * condition between generating and masking interrupts. All we have |
| 138 | * to do is ACK it and return. This is a no-op function so we don't |
| 139 | * need any special tests in the interrupt handler. |
| 140 | */ |
| 141 | static void cpm_error_interrupt (void *dummy) |
| 142 | { |
| 143 | } |
| 144 | |
| 145 | /************************************************************************/ |
| 146 | /* |
| 147 | * Install and free an interrupt handler |
| 148 | */ |
| 149 | void irq_install_handler (int vec, interrupt_handler_t * handler, |
| 150 | void *arg) |
| 151 | { |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 152 | immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 153 | |
| 154 | if ((vec & CPMVEC_OFFSET) != 0) { |
| 155 | /* CPM interrupt */ |
| 156 | vec &= 0xffff; |
| 157 | if (cpm_vecs[vec].handler != NULL) { |
| 158 | printf ("CPM interrupt 0x%x replacing 0x%x\n", |
| 159 | (uint) handler, |
| 160 | (uint) cpm_vecs[vec].handler); |
| 161 | } |
| 162 | cpm_vecs[vec].handler = handler; |
| 163 | cpm_vecs[vec].arg = arg; |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 164 | setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 165 | } else { |
| 166 | /* SIU interrupt */ |
| 167 | if (irq_vecs[vec].handler != NULL) { |
| 168 | printf ("SIU interrupt %d 0x%x replacing 0x%x\n", |
| 169 | vec, |
| 170 | (uint) handler, |
| 171 | (uint) cpm_vecs[vec].handler); |
| 172 | } |
| 173 | irq_vecs[vec].handler = handler; |
| 174 | irq_vecs[vec].arg = arg; |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 175 | setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec)); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 176 | } |
| 177 | } |
| 178 | |
| 179 | void irq_free_handler (int vec) |
| 180 | { |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 181 | immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 182 | |
| 183 | if ((vec & CPMVEC_OFFSET) != 0) { |
| 184 | /* CPM interrupt */ |
| 185 | vec &= 0xffff; |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 186 | clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 187 | cpm_vecs[vec].handler = NULL; |
| 188 | cpm_vecs[vec].arg = NULL; |
| 189 | } else { |
| 190 | /* SIU interrupt */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 191 | clrbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec)); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 192 | irq_vecs[vec].handler = NULL; |
| 193 | irq_vecs[vec].arg = NULL; |
| 194 | } |
| 195 | } |
| 196 | |
| 197 | /************************************************************************/ |
| 198 | |
| 199 | static void cpm_interrupt_init (void) |
| 200 | { |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 201 | immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
| 202 | uint cicr; |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 203 | |
| 204 | /* |
| 205 | * Initialize the CPM interrupt controller. |
| 206 | */ |
| 207 | |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 208 | cicr = CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1 | |
| 209 | ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK; |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 210 | |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 211 | out_be32(&immr->im_cpic.cpic_cicr, cicr); |
| 212 | out_be32(&immr->im_cpic.cpic_cimr, 0); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 213 | |
| 214 | /* |
| 215 | * Install the error handler. |
| 216 | */ |
| 217 | irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL); |
| 218 | |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 219 | setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 220 | |
| 221 | /* |
| 222 | * Install the cpm interrupt handler |
| 223 | */ |
| 224 | irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL); |
| 225 | } |
| 226 | |
| 227 | /************************************************************************/ |
| 228 | |
| 229 | /* |
| 230 | * timer_interrupt - gets called when the decrementer overflows, |
| 231 | * with interrupts disabled. |
| 232 | * Trivial implementation - no need to be really accurate. |
| 233 | */ |
| 234 | void timer_interrupt_cpu (struct pt_regs *regs) |
| 235 | { |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 236 | immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 237 | |
| 238 | /* Reset Timer Expired and Timers Interrupt Status */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 239 | out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 240 | __asm__ ("nop"); |
| 241 | /* |
| 242 | Clear TEXPS (and TMIST on older chips). SPLSS (on older |
| 243 | chips) is cleared too. |
| 244 | |
| 245 | Bitwise OR is a read-modify-write operation so ALL bits |
| 246 | which are cleared by writing `1' would be cleared by |
| 247 | operations like |
| 248 | |
| 249 | immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS; |
| 250 | |
| 251 | The same can be achieved by simple writing of the PLPRCR |
| 252 | to itself. If a bit value should be preserved, read the |
| 253 | register, ZERO the bit and write, not OR, the result back. |
| 254 | */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 255 | setbits_be32(&immr->im_clkrst.car_plprcr, 0); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 256 | } |
| 257 | |
| 258 | /************************************************************************/ |