Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2001 Navin Boppuri / Prashant Patel |
| 3 | * <nboppuri@trinetcommunication.com>, |
| 4 | * <pmpatel@trinetcommunication.com> |
| 5 | * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de> |
| 6 | * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>. |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ |
| 10 | |
| 11 | /* |
| 12 | * MPC8xx CPM SPI interface. |
| 13 | * |
| 14 | * Parts of this code are probably not portable and/or specific to |
| 15 | * the board which I used for the tests. Please send fixes/complaints |
| 16 | * to wd@denx.de |
| 17 | * |
| 18 | */ |
| 19 | |
| 20 | #include <common.h> |
| 21 | #include <mpc8xx.h> |
| 22 | #include <commproc.h> |
| 23 | #include <linux/ctype.h> |
| 24 | #include <malloc.h> |
| 25 | #include <post.h> |
| 26 | #include <serial.h> |
| 27 | |
| 28 | #ifdef CONFIG_SPI |
| 29 | |
| 30 | #define SPI_EEPROM_WREN 0x06 |
| 31 | #define SPI_EEPROM_RDSR 0x05 |
| 32 | #define SPI_EEPROM_READ 0x03 |
| 33 | #define SPI_EEPROM_WRITE 0x02 |
| 34 | |
| 35 | /* --------------------------------------------------------------- |
| 36 | * Offset for initial SPI buffers in DPRAM: |
| 37 | * We need a 520 byte scratch DPRAM area to use at an early stage. |
| 38 | * It is used between the two initialization calls (spi_init_f() |
| 39 | * and spi_init_r()). |
| 40 | * The value 0xb00 makes it far enough from the start of the data |
| 41 | * area (as well as from the stack pointer). |
| 42 | * --------------------------------------------------------------- */ |
| 43 | #ifndef CONFIG_SYS_SPI_INIT_OFFSET |
| 44 | #define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 |
| 45 | #endif |
| 46 | |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 47 | #define CPM_SPI_BASE_RX CPM_SPI_BASE |
| 48 | #define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t)) |
| 49 | |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 50 | /* ------------------- |
| 51 | * Function prototypes |
| 52 | * ------------------- */ |
Christophe Leroy | 70fd071 | 2017-07-06 10:33:17 +0200 | [diff] [blame^] | 53 | ssize_t spi_xfer(size_t); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 54 | |
| 55 | /* ------------------- |
| 56 | * Variables |
| 57 | * ------------------- */ |
| 58 | |
| 59 | #define MAX_BUFFER 0x104 |
| 60 | |
| 61 | /* ---------------------------------------------------------------------- |
| 62 | * Initially we place the RX and TX buffers at a fixed location in DPRAM! |
| 63 | * ---------------------------------------------------------------------- */ |
| 64 | static uchar *rxbuf = |
Christophe Leroy | 70fd071 | 2017-07-06 10:33:17 +0200 | [diff] [blame^] | 65 | (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 66 | [CONFIG_SYS_SPI_INIT_OFFSET]; |
| 67 | static uchar *txbuf = |
Christophe Leroy | 70fd071 | 2017-07-06 10:33:17 +0200 | [diff] [blame^] | 68 | (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 69 | [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER]; |
| 70 | |
| 71 | /* ************************************************************************** |
| 72 | * |
| 73 | * Function: spi_init_f |
| 74 | * |
| 75 | * Description: Init SPI-Controller (ROM part) |
| 76 | * |
| 77 | * return: --- |
| 78 | * |
| 79 | * *********************************************************************** */ |
Christophe Leroy | 70fd071 | 2017-07-06 10:33:17 +0200 | [diff] [blame^] | 80 | void spi_init_f(void) |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 81 | { |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 82 | immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
| 83 | cpm8xx_t __iomem *cp = &immr->im_cpm; |
| 84 | spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; |
| 85 | cbd_t __iomem *tbdf, *rbdf; |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 86 | |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 87 | /* Disable relocation */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 88 | out_be16(&spi->spi_rpbase, 0); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 89 | |
| 90 | /* 1 */ |
| 91 | /* ------------------------------------------------ |
| 92 | * Initialize Port B SPI pins -> page 34-8 MPC860UM |
| 93 | * (we are only in Master Mode !) |
| 94 | * ------------------------------------------------ */ |
| 95 | |
| 96 | /* -------------------------------------------- |
| 97 | * GPIO or per. Function |
| 98 | * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO) |
| 99 | * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI) |
| 100 | * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK) |
| 101 | * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM) |
| 102 | * -------------------------------------------- */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 103 | clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E); /* set bits */ |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 104 | |
| 105 | /* ---------------------------------------------- |
| 106 | * In/Out or per. Function 0/1 |
| 107 | * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO |
| 108 | * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI |
| 109 | * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK |
| 110 | * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM |
| 111 | * ---------------------------------------------- */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 112 | setbits_be32(&cp->cp_pbdir, 0x0000000F); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 113 | |
| 114 | /* ---------------------------------------------- |
| 115 | * open drain or active output |
| 116 | * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO |
| 117 | * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI |
| 118 | * PBODR[30] = 0 [0x00000002] -> active output: SPICLK |
Christophe Leroy | 70fd071 | 2017-07-06 10:33:17 +0200 | [diff] [blame^] | 119 | * PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 120 | * ---------------------------------------------- */ |
| 121 | |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 122 | clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 123 | |
| 124 | /* Initialize the parameter ram. |
| 125 | * We need to make sure many things are initialized to zero |
| 126 | */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 127 | out_be32(&spi->spi_rstate, 0); |
| 128 | out_be32(&spi->spi_rdp, 0); |
| 129 | out_be16(&spi->spi_rbptr, 0); |
| 130 | out_be16(&spi->spi_rbc, 0); |
| 131 | out_be32(&spi->spi_rxtmp, 0); |
| 132 | out_be32(&spi->spi_tstate, 0); |
| 133 | out_be32(&spi->spi_tdp, 0); |
| 134 | out_be16(&spi->spi_tbptr, 0); |
| 135 | out_be16(&spi->spi_tbc, 0); |
| 136 | out_be32(&spi->spi_txtmp, 0); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 137 | |
| 138 | /* 3 */ |
| 139 | /* Set up the SPI parameters in the parameter ram */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 140 | out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX); |
| 141 | out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 142 | |
| 143 | /***********IMPORTANT******************/ |
| 144 | |
| 145 | /* |
| 146 | * Setting transmit and receive buffer descriptor pointers |
| 147 | * initially to rbase and tbase. Only the microcode patches |
| 148 | * documentation talks about initializing this pointer. This |
| 149 | * is missing from the sample I2C driver. If you dont |
| 150 | * initialize these pointers, the kernel hangs. |
| 151 | */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 152 | out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX); |
| 153 | out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 154 | |
| 155 | /* 4 */ |
| 156 | /* Init SPI Tx + Rx Parameters */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 157 | while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 158 | ; |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 159 | |
| 160 | out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | |
| 161 | CPM_CR_FLG); |
| 162 | while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 163 | ; |
| 164 | |
| 165 | /* 5 */ |
| 166 | /* Set SDMA configuration register */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 167 | out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 168 | |
| 169 | /* 6 */ |
| 170 | /* Set to big endian. */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 171 | out_8(&spi->spi_tfcr, SMC_EB); |
| 172 | out_8(&spi->spi_rfcr, SMC_EB); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 173 | |
| 174 | /* 7 */ |
| 175 | /* Set maximum receive size. */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 176 | out_be16(&spi->spi_mrblr, MAX_BUFFER); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 177 | |
| 178 | /* 8 + 9 */ |
| 179 | /* tx and rx buffer descriptors */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 180 | tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; |
| 181 | rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 182 | |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 183 | clrbits_be16(&tbdf->cbd_sc, BD_SC_READY); |
| 184 | clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 185 | |
| 186 | /* Set the bd's rx and tx buffer address pointers */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 187 | out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf); |
| 188 | out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 189 | |
| 190 | /* 10 + 11 */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 191 | out_8(&cp->cp_spim, 0); /* Mask all SPI events */ |
| 192 | out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */ |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 193 | |
| 194 | return; |
| 195 | } |
| 196 | |
| 197 | /* ************************************************************************** |
| 198 | * |
| 199 | * Function: spi_init_r |
| 200 | * |
| 201 | * Description: Init SPI-Controller (RAM part) - |
| 202 | * The malloc engine is ready and we can move our buffers to |
| 203 | * normal RAM |
| 204 | * |
| 205 | * return: --- |
| 206 | * |
| 207 | * *********************************************************************** */ |
Christophe Leroy | 70fd071 | 2017-07-06 10:33:17 +0200 | [diff] [blame^] | 208 | void spi_init_r(void) |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 209 | { |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 210 | immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
| 211 | cpm8xx_t __iomem *cp = &immr->im_cpm; |
| 212 | spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; |
| 213 | cbd_t __iomem *tbdf, *rbdf; |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 214 | |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 215 | /* Disable relocation */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 216 | out_be16(&spi->spi_rpbase, 0); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 217 | |
| 218 | /* tx and rx buffer descriptors */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 219 | tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; |
| 220 | rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 221 | |
| 222 | /* Allocate memory for RX and TX buffers */ |
Christophe Leroy | 70fd071 | 2017-07-06 10:33:17 +0200 | [diff] [blame^] | 223 | rxbuf = (uchar *)malloc(MAX_BUFFER); |
| 224 | txbuf = (uchar *)malloc(MAX_BUFFER); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 225 | |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 226 | out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf); |
| 227 | out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 228 | |
| 229 | return; |
| 230 | } |
| 231 | |
| 232 | /**************************************************************************** |
| 233 | * Function: spi_write |
| 234 | **************************************************************************** */ |
Christophe Leroy | 70fd071 | 2017-07-06 10:33:17 +0200 | [diff] [blame^] | 235 | ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 236 | { |
| 237 | int i; |
| 238 | |
| 239 | memset(rxbuf, 0, MAX_BUFFER); |
| 240 | memset(txbuf, 0, MAX_BUFFER); |
| 241 | *txbuf = SPI_EEPROM_WREN; /* write enable */ |
| 242 | spi_xfer(1); |
| 243 | memcpy(txbuf, addr, alen); |
| 244 | *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ |
| 245 | memcpy(alen + txbuf, buffer, len); |
| 246 | spi_xfer(alen + len); |
| 247 | /* ignore received data */ |
| 248 | for (i = 0; i < 1000; i++) { |
| 249 | *txbuf = SPI_EEPROM_RDSR; /* read status */ |
| 250 | txbuf[1] = 0; |
| 251 | spi_xfer(2); |
Christophe Leroy | 70fd071 | 2017-07-06 10:33:17 +0200 | [diff] [blame^] | 252 | if (!(rxbuf[1] & 1)) |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 253 | break; |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 254 | udelay(1000); |
| 255 | } |
Christophe Leroy | 70fd071 | 2017-07-06 10:33:17 +0200 | [diff] [blame^] | 256 | if (i >= 1000) |
| 257 | printf("*** spi_write: Time out while writing!\n"); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 258 | |
| 259 | return len; |
| 260 | } |
| 261 | |
| 262 | /**************************************************************************** |
| 263 | * Function: spi_read |
| 264 | **************************************************************************** */ |
Christophe Leroy | 70fd071 | 2017-07-06 10:33:17 +0200 | [diff] [blame^] | 265 | ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 266 | { |
| 267 | memset(rxbuf, 0, MAX_BUFFER); |
| 268 | memset(txbuf, 0, MAX_BUFFER); |
| 269 | memcpy(txbuf, addr, alen); |
| 270 | *txbuf = SPI_EEPROM_READ; /* READ memory array */ |
| 271 | |
| 272 | /* |
| 273 | * There is a bug in 860T (?) that cuts the last byte of input |
| 274 | * if we're reading into DPRAM. The solution we choose here is |
| 275 | * to always read len+1 bytes (we have one extra byte at the |
| 276 | * end of the buffer). |
| 277 | */ |
| 278 | spi_xfer(alen + len + 1); |
| 279 | memcpy(buffer, alen + rxbuf, len); |
| 280 | |
| 281 | return len; |
| 282 | } |
| 283 | |
| 284 | /**************************************************************************** |
| 285 | * Function: spi_xfer |
| 286 | **************************************************************************** */ |
Christophe Leroy | 70fd071 | 2017-07-06 10:33:17 +0200 | [diff] [blame^] | 287 | ssize_t spi_xfer(size_t count) |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 288 | { |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 289 | immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
| 290 | cpm8xx_t __iomem *cp = &immr->im_cpm; |
| 291 | spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; |
| 292 | cbd_t __iomem *tbdf, *rbdf; |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 293 | int tm; |
| 294 | |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 295 | /* Disable relocation */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 296 | out_be16(&spi->spi_rpbase, 0); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 297 | |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 298 | tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; |
| 299 | rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 300 | |
| 301 | /* Set CS for device */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 302 | clrbits_be32(&cp->cp_pbdat, 0x0001); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 303 | |
| 304 | /* Setting tx bd status and data length */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 305 | out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP); |
| 306 | out_be16(&tbdf->cbd_datlen, count); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 307 | |
| 308 | /* Setting rx bd status and data length */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 309 | out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP); |
| 310 | out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */ |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 311 | |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 312 | clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR | |
| 313 | SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8)); |
| 314 | out_8(&cp->cp_spim, 0); /* Mask all SPI events */ |
| 315 | out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */ |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 316 | |
| 317 | /* start spi transfer */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 318 | setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */ |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 319 | |
| 320 | /* -------------------------------- |
| 321 | * Wait for SPI transmit to get out |
| 322 | * or time out (1 second = 1000 ms) |
| 323 | * -------------------------------- */ |
Christophe Leroy | 70fd071 | 2017-07-06 10:33:17 +0200 | [diff] [blame^] | 324 | for (tm = 0; tm < 1000; ++tm) { |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 325 | if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */ |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 326 | break; |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 327 | if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0) |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 328 | break; |
Christophe Leroy | 70fd071 | 2017-07-06 10:33:17 +0200 | [diff] [blame^] | 329 | udelay(1000); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 330 | } |
Christophe Leroy | 70fd071 | 2017-07-06 10:33:17 +0200 | [diff] [blame^] | 331 | if (tm >= 1000) |
| 332 | printf("*** spi_xfer: Time out while xferring to/from SPI!\n"); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 333 | |
| 334 | /* Clear CS for device */ |
Christophe Leroy | ba3da73 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 335 | setbits_be32(&cp->cp_pbdat, 0x0001); |
Christophe Leroy | 907208c | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 336 | |
| 337 | return count; |
| 338 | } |
| 339 | #endif /* CONFIG_SPI */ |