blob: 21259634075f27a47f0432b37f770ee60e7f339a [file] [log] [blame]
wdenk67c4f482002-08-26 22:23:10 +00001/*
wdenkdb2f721f2003-03-06 00:58:30 +00002 * (C) Copyright 2001-2003
wdenk67c4f482002-08-26 22:23:10 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Modified during 2001 by
6 * Advanced Communications Technologies (Australia) Pty. Ltd.
7 * Howard Walker, Tuong Vu-Dinh
8 *
9 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
10 * Added support for the 16M dram simm on the 8260ads boards
11 *
wdenk04a85b32004-04-15 18:22:41 +000012 * (C) Copyright 2003-2004 Arabella Software Ltd.
wdenk48b42612003-06-19 23:01:32 +000013 * Yuli Barcohen <yuli@arabellasw.com>
14 * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
15 *
Wolfgang Denk1972dc02005-09-25 16:27:55 +020016 * Copyright (c) 2005 MontaVista Software, Inc.
17 * Vitaly Bordug <vbordug@ru.mvista.com>
18 * Added support for PCI.
19 *
wdenk67c4f482002-08-26 22:23:10 +000020 * See file CREDITS for list of people who contributed to this
21 * project.
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License as
25 * published by the Free Software Foundation; either version 2 of
26 * the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 * MA 02111-1307 USA
37 */
38
39#include <common.h>
40#include <ioports.h>
41#include <mpc8260.h>
wdenk326428c2003-08-31 18:37:54 +000042#include <asm/m8260_pci.h>
wdenkdb2f721f2003-03-06 00:58:30 +000043#include <i2c.h>
44#include <spd.h>
wdenkcceb8712003-06-23 18:12:28 +000045#include <miiphy.h>
Wolfgang Denk1972dc02005-09-25 16:27:55 +020046#ifdef CONFIG_PCI
47#include <pci.h>
48#endif
wdenk67c4f482002-08-26 22:23:10 +000049
50/*
51 * I/O Port configuration table
52 *
53 * if conf is 1, then that port pin will be configured at boot time
54 * according to the five values podr/pdir/ppar/psor/pdat for that entry
55 */
56
wdenk04a85b32004-04-15 18:22:41 +000057#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
58#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
59#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
60
wdenk67c4f482002-08-26 22:23:10 +000061const iop_conf_t iop_conf_tab[4][32] = {
62
63 /* Port A configuration */
wdenk04a85b32004-04-15 18:22:41 +000064 { /* conf ppar psor pdir podr pdat */
65 /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
66 /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
67 /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
68 /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
69 /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
70 /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
71 /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
72 /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
73 /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
74 /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
75 /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
76 /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
77 /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
78 /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
79 /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
80 /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
81 /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
82 /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
83 /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
84 /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
85 /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
86 /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
87 /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */
88 /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */
89 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
90 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
91 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
92 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
93 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
94 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
95 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
96 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
wdenk67c4f482002-08-26 22:23:10 +000097 },
98
99 /* Port B configuration */
wdenk04a85b32004-04-15 18:22:41 +0000100 { /* conf ppar psor pdir podr pdat */
101 /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
102 /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
103 /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
104 /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
105 /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
106 /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
107 /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
108 /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
109 /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
110 /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
111 /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
112 /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
113 /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
114 /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
115 /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
116 /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
117 /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
118 /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
119 /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
120 /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
121 /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
122 /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
123 /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
124 /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
125 /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
126 /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
127 /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
128 /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
129 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
130 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
131 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
132 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
wdenk67c4f482002-08-26 22:23:10 +0000133 },
134
135 /* Port C */
wdenk04a85b32004-04-15 18:22:41 +0000136 { /* conf ppar psor pdir podr pdat */
137 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
138 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
139 /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
140 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
141 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
142 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
143 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
144 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
145 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
146 /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */
147 /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */
148 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
149#if CONFIG_ADSTYPE == CFG_8272ADS
150 /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
151 /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
152 /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */
153 /* PC16 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */
154#else
155 /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
156 /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
157 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
158 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
159#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
160 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
161 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
162 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
163 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
164 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
165#if CONFIG_ADSTYPE == CFG_8272ADS
166 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
167 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
168#else
169 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
170 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
171#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
172 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
173 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
174 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
175 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
176 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
177 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
178 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
179 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
180 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
wdenk67c4f482002-08-26 22:23:10 +0000181 },
182
183 /* Port D */
184 { /* conf ppar psor pdir podr pdat */
wdenkcceb8712003-06-23 18:12:28 +0000185 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
186 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
wdenk04a85b32004-04-15 18:22:41 +0000187 /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
wdenk67c4f482002-08-26 22:23:10 +0000188 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
189 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
190 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
191 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
192 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
193 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
194 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
195 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
196 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
197 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
198 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
199 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
200 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
wdenkcceb8712003-06-23 18:12:28 +0000201 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
202 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
wdenk67c4f482002-08-26 22:23:10 +0000203 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
204 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
205 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
206 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
wdenkcceb8712003-06-23 18:12:28 +0000207 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
208 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
wdenk67c4f482002-08-26 22:23:10 +0000209 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
210 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
211 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
212 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
213 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
214 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
215 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
216 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
217 }
218};
219
wdenkdb2f721f2003-03-06 00:58:30 +0000220void reset_phy (void)
wdenk67c4f482002-08-26 22:23:10 +0000221{
wdenkcceb8712003-06-23 18:12:28 +0000222 vu_long *bcsr = (vu_long *)CFG_BCSR;
wdenk67c4f482002-08-26 22:23:10 +0000223
wdenk04a85b32004-04-15 18:22:41 +0000224 /* Reset the PHY */
225#if CFG_PHY_ADDR == 0
226 bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
wdenkcceb8712003-06-23 18:12:28 +0000227 udelay(2);
wdenk2535d602003-07-17 23:16:40 +0000228 bcsr[1] |= FETH1_RST;
wdenk04a85b32004-04-15 18:22:41 +0000229#else
230 bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
231 udelay(2);
232 bcsr[3] |= FETH2_RST;
233#endif /* CFG_PHY_ADDR == 0 */
wdenkcceb8712003-06-23 18:12:28 +0000234 udelay(1000);
235#ifdef CONFIG_MII
wdenk04a85b32004-04-15 18:22:41 +0000236#if CONFIG_ADSTYPE >= CFG_PQ2FADS
wdenk2535d602003-07-17 23:16:40 +0000237 /*
238 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
239 * Enable autonegotiation.
240 */
wdenk04a85b32004-04-15 18:22:41 +0000241 miiphy_write(CFG_PHY_ADDR, 16, 0x610);
242 miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
wdenk2535d602003-07-17 23:16:40 +0000243#else
wdenkcceb8712003-06-23 18:12:28 +0000244 /*
245 * Ethernet PHY is configured (by means of configuration pins)
246 * to work at 10Mb/s only. We reconfigure it using MII
247 * to advertise all capabilities, including 100Mb/s, and
248 * restart autonegotiation.
249 */
wdenk04a85b32004-04-15 18:22:41 +0000250 miiphy_write(CFG_PHY_ADDR, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
251 miiphy_write(CFG_PHY_ADDR, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */
252 miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
wdenk2535d602003-07-17 23:16:40 +0000253#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
wdenkcceb8712003-06-23 18:12:28 +0000254#endif /* CONFIG_MII */
wdenk67c4f482002-08-26 22:23:10 +0000255}
256
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200257#ifdef CONFIG_PCI
258typedef struct pci_ic_s {
259 unsigned long pci_int_stat;
260 unsigned long pci_int_mask;
261}pci_ic_t;
262#endif
263
wdenkc837dcb2004-01-20 23:12:12 +0000264int board_early_init_f (void)
wdenk67c4f482002-08-26 22:23:10 +0000265{
wdenkcceb8712003-06-23 18:12:28 +0000266 vu_long *bcsr = (vu_long *)CFG_BCSR;
wdenk67c4f482002-08-26 22:23:10 +0000267
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200268#ifdef CONFIG_PCI
269 volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT;
270
271 /* mask alll the PCI interrupts */
272 pci_ic->pci_int_mask |= 0xfff00000;
273#endif
wdenk04a85b32004-04-15 18:22:41 +0000274#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
275 bcsr[1] &= ~RS232EN_1;
276#endif
277#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
278 bcsr[1] &= ~RS232EN_2;
279#endif
wdenkdb2f721f2003-03-06 00:58:30 +0000280
wdenkef5a9672003-12-07 00:46:27 +0000281#if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */
282#if CONFIG_ADSTYPE == CFG_PQ2FADS
283 if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
284#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
285 {
286 volatile immap_t *immap = (immap_t *) CFG_IMMR;
287
288 immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
289 immap->im_siu_conf.sc_siumcr =
290 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
291 | SIUMCR_LBPC01;
292 }
293#endif /* CONFIG_ADSTYPE != CFG_8260ADS */
294
wdenkdb2f721f2003-03-06 00:58:30 +0000295 return 0;
wdenk67c4f482002-08-26 22:23:10 +0000296}
297
wdenkdb2f721f2003-03-06 00:58:30 +0000298#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
299
300long int initdram (int board_type)
wdenk67c4f482002-08-26 22:23:10 +0000301{
wdenk04a85b32004-04-15 18:22:41 +0000302#if CONFIG_ADSTYPE == CFG_PQ2FADS
wdenkef5a9672003-12-07 00:46:27 +0000303 long int msize = 32;
wdenk04a85b32004-04-15 18:22:41 +0000304#elif CONFIG_ADSTYPE == CFG_8272ADS
305 long int msize = 64;
wdenkef5a9672003-12-07 00:46:27 +0000306#else
307 long int msize = 16;
wdenk149dded2003-09-10 18:20:28 +0000308#endif
wdenkef5a9672003-12-07 00:46:27 +0000309
310#ifndef CFG_RAMBOOT
wdenkdb2f721f2003-03-06 00:58:30 +0000311 volatile immap_t *immap = (immap_t *) CFG_IMMR;
312 volatile memctl8260_t *memctl = &immap->im_memctl;
313 volatile uchar *ramaddr, c = 0xff;
wdenk2535d602003-07-17 23:16:40 +0000314 uint or;
315 uint psdmr;
316 uint psrt;
wdenkdb2f721f2003-03-06 00:58:30 +0000317
318 int i;
wdenk67c4f482002-08-26 22:23:10 +0000319
wdenkdb2f721f2003-03-06 00:58:30 +0000320 immap->im_siu_conf.sc_ppc_acr = 0x00000002;
321 immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
322 immap->im_siu_conf.sc_tescr1 = 0x00004000;
wdenk67c4f482002-08-26 22:23:10 +0000323
wdenkdb2f721f2003-03-06 00:58:30 +0000324 memctl->memc_mptpr = CFG_MPTPR;
wdenk2535d602003-07-17 23:16:40 +0000325#ifdef CFG_LSDRAM_BASE
wdenk326428c2003-08-31 18:37:54 +0000326 /*
327 Initialise local bus SDRAM only if the pins
328 are configured as local bus pins and not as PCI.
329 The configuration is determined by the HRCW.
330 */
331 if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
332 memctl->memc_lsrt = CFG_LSRT;
wdenk2535d602003-07-17 23:16:40 +0000333#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
wdenk326428c2003-08-31 18:37:54 +0000334 memctl->memc_or3 = 0xFF803280;
335 memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861;
wdenk2535d602003-07-17 23:16:40 +0000336#else /* CS4 */
wdenk326428c2003-08-31 18:37:54 +0000337 memctl->memc_or4 = 0xFFC01480;
338 memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
wdenk2535d602003-07-17 23:16:40 +0000339#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
wdenk326428c2003-08-31 18:37:54 +0000340 memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
341 ramaddr = (uchar *) CFG_LSDRAM_BASE;
wdenkdb2f721f2003-03-06 00:58:30 +0000342 *ramaddr = c;
wdenk326428c2003-08-31 18:37:54 +0000343 memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
344 for (i = 0; i < 8; i++)
345 *ramaddr = c;
346 memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
347 *ramaddr = c;
348 memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
wdenkdb2f721f2003-03-06 00:58:30 +0000349 }
wdenk2535d602003-07-17 23:16:40 +0000350#endif /* CFG_LSDRAM_BASE */
wdenk67c4f482002-08-26 22:23:10 +0000351
wdenk2535d602003-07-17 23:16:40 +0000352 /* Init 60x bus SDRAM */
wdenkdb2f721f2003-03-06 00:58:30 +0000353#ifdef CONFIG_SPD_EEPROM
354 {
355 spd_eeprom_t spd;
356 uint pbi, bsel, rowst, lsb, tmp;
wdenk67c4f482002-08-26 22:23:10 +0000357
wdenkdb2f721f2003-03-06 00:58:30 +0000358 i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
359
360 /* Bank-based interleaving is not supported for physical bank
361 sizes greater than 128MB which is encoded as 0x20 in SPD
362 */
363 pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
364 msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
365 or = ~(msize - 1) << 20; /* SDAM */
366 switch (spd.nbanks) { /* BPD */
367 case 2:
368 bsel = 1;
369 break;
370 case 4:
371 bsel = 2;
372 or |= 0x00002000;
373 break;
374 case 8:
375 bsel = 3;
376 or |= 0x00004000;
377 break;
378 }
379 lsb = 3; /* For 64-bit port, lsb is 3 bits */
380
381 if (pbi) { /* Bus partition depends on interleaving */
382 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
383 or |= (rowst << 9); /* ROWST */
384 } else {
385 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
386 or |= ((rowst * 2 - 12) << 9); /* ROWST */
387 }
388 or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
389
390 psdmr = (pbi << 31); /* PBI */
391 /* Bus multiplexing parameters */
392 tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
393 psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
394 psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
395
396 tmp = (31 - lsb - 10) - tmp;
397 /* Pin connected to SDA10 is (31 - lsb - 10).
398 rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
399 so (rowst + tmp) alternates with AP.
400 */
401 if (pbi) /* Table 10-7 */
402 psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
403 else
404 psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
405
406 /* SDRAM device-specific parameters */
407 tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
408 switch (tmp) { /* RFRC */
409 case 1:
410 case 2:
411 psdmr |= (1 << 15);
412 break;
413 case 3:
414 case 4:
415 case 5:
416 case 6:
417 case 7:
418 case 8:
419 psdmr |= ((tmp - 2) << 15);
420 break;
421 default:
422 psdmr |= (7 << 15);
423 }
424 psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
425 psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
426 /* BL=0 because for 64-bit SDRAM burst length must be 4 */
427 /* LDOTOPRE ??? */
428 for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
429 tmp >>= 1;
430 switch (i) { /* WRC */
431 case 0:
432 case 1:
433 psdmr |= (1 << 4);
434 break;
435 case 2:
436 case 3:
437 psdmr |= (i << 4);
438 break;
439 }
440 /* EAMUX=0 - no external address multiplexing */
441 /* BUFCMD=0 - no external buffers */
442 for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
443 tmp >>= 1;
444 psdmr |= i; /* CL */
445
446 switch (spd.refresh & 0x7F) {
447 case 1:
448 tmp = 3900;
449 break;
450 case 2:
451 tmp = 7800;
452 break;
453 case 3:
454 tmp = 31300;
455 break;
456 case 4:
457 tmp = 62500;
458 break;
459 case 5:
460 tmp = 125000;
461 break;
462 default:
463 tmp = 15625;
464 }
465 psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
466 ((memctl->memc_mptpr >> 8) + 1)) - 1;
467#ifdef SPD_DEBUG
468 printf ("\nDIMM type: %-18.18s\n", spd.mpart);
469 printf ("SPD size: %d\n", spd.info_size);
470 printf ("EEPROM size: %d\n", 1 << spd.chip_size);
471 printf ("Memory type: %d\n", spd.mem_type);
472 printf ("Row addr: %d\n", spd.nrow_addr);
473 printf ("Column addr: %d\n", spd.ncol_addr);
474 printf ("# of rows: %d\n", spd.nrows);
475 printf ("Row density: %d\n", spd.row_dens);
476 printf ("# of banks: %d\n", spd.nbanks);
477 printf ("Data width: %d\n",
478 256 * spd.dataw_msb + spd.dataw_lsb);
479 printf ("Chip width: %d\n", spd.primw);
480 printf ("Refresh rate: %02X\n", spd.refresh);
481 printf ("CAS latencies: %02X\n", spd.cas_lat);
482 printf ("Write latencies: %02X\n", spd.write_lat);
483 printf ("tRP: %d\n", spd.trp);
484 printf ("tRCD: %d\n", spd.trcd);
485
486 printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
487#endif /* SPD_DEBUG */
488 }
wdenk2535d602003-07-17 23:16:40 +0000489#else /* !CONFIG_SPD_EEPROM */
wdenkef5a9672003-12-07 00:46:27 +0000490 or = CFG_OR2;
wdenk2535d602003-07-17 23:16:40 +0000491 psdmr = CFG_PSDMR;
492 psrt = CFG_PSRT;
wdenkdb2f721f2003-03-06 00:58:30 +0000493#endif /* CONFIG_SPD_EEPROM */
494 memctl->memc_psrt = psrt;
495 memctl->memc_or2 = or;
496 memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
497 ramaddr = (uchar *) CFG_SDRAM_BASE;
498 memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
499 *ramaddr = c;
500 memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
501 for (i = 0; i < 8; i++)
502 *ramaddr = c;
503
504 memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
505 *ramaddr = c;
506 memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
507 *ramaddr = c;
wdenkef5a9672003-12-07 00:46:27 +0000508#endif /* CFG_RAMBOOT */
wdenk67c4f482002-08-26 22:23:10 +0000509
wdenk2535d602003-07-17 23:16:40 +0000510 /* return total 60x bus SDRAM size */
wdenkdb2f721f2003-03-06 00:58:30 +0000511 return (msize * 1024 * 1024);
wdenk67c4f482002-08-26 22:23:10 +0000512}
513
wdenkdb2f721f2003-03-06 00:58:30 +0000514int checkboard (void)
wdenk67c4f482002-08-26 22:23:10 +0000515{
wdenk2535d602003-07-17 23:16:40 +0000516#if CONFIG_ADSTYPE == CFG_8260ADS
wdenkdb2f721f2003-03-06 00:58:30 +0000517 puts ("Board: Motorola MPC8260ADS\n");
wdenk2535d602003-07-17 23:16:40 +0000518#elif CONFIG_ADSTYPE == CFG_8266ADS
519 puts ("Board: Motorola MPC8266ADS\n");
520#elif CONFIG_ADSTYPE == CFG_PQ2FADS
521 puts ("Board: Motorola PQ2FADS-ZU\n");
wdenk04a85b32004-04-15 18:22:41 +0000522#elif CONFIG_ADSTYPE == CFG_8272ADS
523 puts ("Board: Motorola MPC8272ADS\n");
wdenk2535d602003-07-17 23:16:40 +0000524#else
525 puts ("Board: unknown\n");
526#endif
wdenkdb2f721f2003-03-06 00:58:30 +0000527 return 0;
wdenk67c4f482002-08-26 22:23:10 +0000528}
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200529
530#ifdef CONFIG_PCI
531struct pci_controller hose;
532
533extern void pci_mpc8250_init(struct pci_controller *);
534
535void pci_init_board(void)
536{
537 pci_mpc8250_init(&hose);
538}
539#endif