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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * MPC8xx Communication Processor Module.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
Wolfgang Denk8cba0902006-05-12 16:15:46 +02005 * (C) Copyright 2000-2006
wdenkd4ca31c2004-01-02 14:00:00 +00006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
wdenkfe8c2802002-11-03 00:38:21 +00008 * This file contains structures and information for the communication
9 * processor channels. Some CPM control and status is available
10 * throught the MPC8xx internal memory map. See immap.h for details.
11 * This file only contains what I need for the moment, not the total
12 * CPM capabilities. I (or someone else) will add definitions as they
13 * are needed. -- Dan
14 *
15 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
16 * bytes of the DP RAM and relocates the I2C parameter area to the
17 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
18 * or other use.
19 */
20#ifndef __CPM_8XX__
21#define __CPM_8XX__
22
23#include <linux/config.h>
24#include <asm/8xx_immap.h>
25
26/* CPM Command register.
27*/
wdenk7c7a23b2002-12-07 00:20:59 +000028#define CPM_CR_RST ((ushort)0x8000)
29#define CPM_CR_OPCODE ((ushort)0x0f00)
30#define CPM_CR_CHAN ((ushort)0x00f0)
31#define CPM_CR_FLG ((ushort)0x0001)
wdenkfe8c2802002-11-03 00:38:21 +000032
33/* Some commands (there are more...later)
34*/
35#define CPM_CR_INIT_TRX ((ushort)0x0000)
36#define CPM_CR_INIT_RX ((ushort)0x0001)
37#define CPM_CR_INIT_TX ((ushort)0x0002)
38#define CPM_CR_HUNT_MODE ((ushort)0x0003)
39#define CPM_CR_STOP_TX ((ushort)0x0004)
40#define CPM_CR_RESTART_TX ((ushort)0x0006)
41#define CPM_CR_SET_GADDR ((ushort)0x0008)
42
43/* Channel numbers.
44*/
wdenk7c7a23b2002-12-07 00:20:59 +000045#define CPM_CR_CH_SCC1 ((ushort)0x0000)
46#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
47#define CPM_CR_CH_SCC2 ((ushort)0x0004)
48#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */
49#define CPM_CR_CH_SCC3 ((ushort)0x0008)
50#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
51#define CPM_CR_CH_SCC4 ((ushort)0x000c)
52#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
wdenkfe8c2802002-11-03 00:38:21 +000053
54#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
55
56/*
57 * DPRAM defines and allocation functions
58 */
59
60/* The dual ported RAM is multi-functional. Some areas can be (and are
61 * being) used for microcode. There is an area that can only be used
62 * as data ram for buffer descriptors, which is all we use right now.
63 * Currently the first 512 and last 256 bytes are used for microcode.
64 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#ifdef CONFIG_SYS_ALLOC_DPRAM
wdenkfe8c2802002-11-03 00:38:21 +000066
67#define CPM_DATAONLY_BASE ((uint)0x0800)
68#define CPM_DATAONLY_SIZE ((uint)0x0700)
69#define CPM_DP_NOSPACE ((uint)0x7fffffff)
70
71#else
72
73#define CPM_SERIAL_BASE 0x0800
74#define CPM_I2C_BASE 0x0820
75#define CPM_SPI_BASE 0x0840
76#define CPM_FEC_BASE 0x0860
wdenk79536a62004-09-27 20:20:11 +000077#define CPM_SERIAL2_BASE 0x08E0
wdenkfe8c2802002-11-03 00:38:21 +000078#define CPM_SCC_BASE 0x0900
79#define CPM_POST_BASE 0x0980
wdenk281e00a2004-08-01 22:48:16 +000080#define CPM_WLKBD_BASE 0x0a00
wdenkfe8c2802002-11-03 00:38:21 +000081
82#endif
83
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
wdenkfe8c2802002-11-03 00:38:21 +000085#define CPM_POST_WORD_ADDR 0x07FC
wdenkea909b72002-11-21 23:11:29 +000086#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR
wdenkea909b72002-11-21 23:11:29 +000088#endif
wdenkfe8c2802002-11-03 00:38:21 +000089
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
wdenkbdccc4f2003-08-05 17:43:17 +000091#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
92#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR
wdenkbdccc4f2003-08-05 17:43:17 +000094#endif
95
wdenkfe8c2802002-11-03 00:38:21 +000096#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
97
98/* Export the base address of the communication processor registers
99 * and dual port ram.
100 */
101extern cpm8xx_t *cpmp; /* Pointer to comm processor */
102
103/* Buffer descriptors used by many of the CPM protocols.
104*/
105typedef struct cpm_buf_desc {
106 ushort cbd_sc; /* Status and Control */
107 ushort cbd_datlen; /* Data length in buffer */
108 uint cbd_bufaddr; /* Buffer address in host memory */
109} cbd_t;
110
111#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
112#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
113#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
114#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
115#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
116#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
117#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
118#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
119#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
120#define BD_SC_BR ((ushort)0x0020) /* Break received */
121#define BD_SC_FR ((ushort)0x0010) /* Framing error */
122#define BD_SC_PR ((ushort)0x0008) /* Parity error */
123#define BD_SC_OV ((ushort)0x0002) /* Overrun */
124#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
125
126/* Parameter RAM offsets.
127*/
128#define PROFF_SCC1 ((uint)0x0000)
129#define PROFF_IIC ((uint)0x0080)
130#define PROFF_SCC2 ((uint)0x0100)
131#define PROFF_SPI ((uint)0x0180)
132#define PROFF_SCC3 ((uint)0x0200)
133#define PROFF_SMC1 ((uint)0x0280)
134#define PROFF_SCC4 ((uint)0x0300)
135#define PROFF_SMC2 ((uint)0x0380)
136
137/* Define enough so I can at least use the serial port as a UART.
138 * The MBX uses SMC1 as the host serial port.
139 */
140typedef struct smc_uart {
141 ushort smc_rbase; /* Rx Buffer descriptor base address */
142 ushort smc_tbase; /* Tx Buffer descriptor base address */
143 u_char smc_rfcr; /* Rx function code */
144 u_char smc_tfcr; /* Tx function code */
145 ushort smc_mrblr; /* Max receive buffer length */
146 uint smc_rstate; /* Internal */
147 uint smc_idp; /* Internal */
148 ushort smc_rbptr; /* Internal */
149 ushort smc_ibc; /* Internal */
150 uint smc_rxtmp; /* Internal */
151 uint smc_tstate; /* Internal */
152 uint smc_tdp; /* Internal */
153 ushort smc_tbptr; /* Internal */
154 ushort smc_tbc; /* Internal */
155 uint smc_txtmp; /* Internal */
156 ushort smc_maxidl; /* Maximum idle characters */
157 ushort smc_tmpidl; /* Temporary idle counter */
158 ushort smc_brklen; /* Last received break length */
159 ushort smc_brkec; /* rcv'd break condition counter */
160 ushort smc_brkcr; /* xmt break count register */
161 ushort smc_rmask; /* Temporary bit mask */
Heiko Schocherb423d052008-01-11 01:12:07 +0100162 u_char res1[8];
163 ushort smc_rpbase; /* Relocation pointer */
wdenkfe8c2802002-11-03 00:38:21 +0000164} smc_uart_t;
165
166/* Function code bits.
167*/
168#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
169
170/* SMC uart mode register.
171*/
172#define SMCMR_REN ((ushort)0x0001)
173#define SMCMR_TEN ((ushort)0x0002)
174#define SMCMR_DM ((ushort)0x000c)
175#define SMCMR_SM_GCI ((ushort)0x0000)
176#define SMCMR_SM_UART ((ushort)0x0020)
177#define SMCMR_SM_TRANS ((ushort)0x0030)
178#define SMCMR_SM_MASK ((ushort)0x0030)
179#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
180#define SMCMR_REVD SMCMR_PM_EVEN
181#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
182#define SMCMR_BS SMCMR_PEN
183#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
184#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
185#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
186
187/* SMC2 as Centronics parallel printer. It is half duplex, in that
188 * it can only receive or transmit. The parameter ram values for
189 * each direction are either unique or properly overlap, so we can
190 * include them in one structure.
191 */
192typedef struct smc_centronics {
193 ushort scent_rbase;
194 ushort scent_tbase;
195 u_char scent_cfcr;
196 u_char scent_smask;
197 ushort scent_mrblr;
198 uint scent_rstate;
199 uint scent_r_ptr;
200 ushort scent_rbptr;
201 ushort scent_r_cnt;
202 uint scent_rtemp;
203 uint scent_tstate;
204 uint scent_t_ptr;
205 ushort scent_tbptr;
206 ushort scent_t_cnt;
207 uint scent_ttemp;
208 ushort scent_max_sl;
209 ushort scent_sl_cnt;
210 ushort scent_character1;
211 ushort scent_character2;
212 ushort scent_character3;
213 ushort scent_character4;
214 ushort scent_character5;
215 ushort scent_character6;
216 ushort scent_character7;
217 ushort scent_character8;
218 ushort scent_rccm;
219 ushort scent_rccr;
220} smc_cent_t;
221
222/* Centronics Status Mask Register.
223*/
224#define SMC_CENT_F ((u_char)0x08)
225#define SMC_CENT_PE ((u_char)0x04)
226#define SMC_CENT_S ((u_char)0x02)
227
228/* SMC Event and Mask register.
229*/
230#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
231#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
232#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
233#define SMCM_BSY ((unsigned char)0x04)
234#define SMCM_TX ((unsigned char)0x02)
235#define SMCM_RX ((unsigned char)0x01)
236
237/* Baud rate generators.
238*/
239#define CPM_BRG_RST ((uint)0x00020000)
240#define CPM_BRG_EN ((uint)0x00010000)
241#define CPM_BRG_EXTC_INT ((uint)0x00000000)
242#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
243#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
244#define CPM_BRG_ATB ((uint)0x00002000)
245#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
246#define CPM_BRG_DIV16 ((uint)0x00000001)
247
248/* SI Clock Route Register
249*/
250#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
251#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
252#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
253#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
254#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
255#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
256#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
257#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
258
259/* SCCs.
260*/
261#define SCC_GSMRH_IRP ((uint)0x00040000)
262#define SCC_GSMRH_GDE ((uint)0x00010000)
263#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
264#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
265#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
266#define SCC_GSMRH_REVD ((uint)0x00002000)
267#define SCC_GSMRH_TRX ((uint)0x00001000)
268#define SCC_GSMRH_TTX ((uint)0x00000800)
269#define SCC_GSMRH_CDP ((uint)0x00000400)
270#define SCC_GSMRH_CTSP ((uint)0x00000200)
271#define SCC_GSMRH_CDS ((uint)0x00000100)
272#define SCC_GSMRH_CTSS ((uint)0x00000080)
273#define SCC_GSMRH_TFL ((uint)0x00000040)
274#define SCC_GSMRH_RFW ((uint)0x00000020)
275#define SCC_GSMRH_TXSY ((uint)0x00000010)
276#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
277#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
278#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
279#define SCC_GSMRH_RTSM ((uint)0x00000002)
280#define SCC_GSMRH_RSYN ((uint)0x00000001)
281
282#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
283#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
284#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
285#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
286#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
287#define SCC_GSMRL_TCI ((uint)0x10000000)
288#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
289#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
290#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
291#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
292#define SCC_GSMRL_RINV ((uint)0x02000000)
293#define SCC_GSMRL_TINV ((uint)0x01000000)
294#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
295#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
296#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
297#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
298#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
299#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
300#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
301#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
302#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
303#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
304#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
305#define SCC_GSMRL_TEND ((uint)0x00040000)
306#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
307#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
308#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
309#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
310#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
311#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
312#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
313#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
314#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
315#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
316#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
317#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
318#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
319#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
320#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
321#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
322#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
323#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
324#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
325#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
326#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
327#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
328#define SCC_GSMRL_ENR ((uint)0x00000020)
329#define SCC_GSMRL_ENT ((uint)0x00000010)
330#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
331#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
332#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
333#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
334#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
335#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
336#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
337#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
338#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
339#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
340
341#define SCC_TODR_TOD ((ushort)0x8000)
342
343/* SCC Event and Mask register.
344*/
345#define SCCM_TXE ((unsigned char)0x10)
346#define SCCM_BSY ((unsigned char)0x04)
347#define SCCM_TX ((unsigned char)0x02)
348#define SCCM_RX ((unsigned char)0x01)
349
350typedef struct scc_param {
351 ushort scc_rbase; /* Rx Buffer descriptor base address */
352 ushort scc_tbase; /* Tx Buffer descriptor base address */
353 u_char scc_rfcr; /* Rx function code */
354 u_char scc_tfcr; /* Tx function code */
355 ushort scc_mrblr; /* Max receive buffer length */
356 uint scc_rstate; /* Internal */
357 uint scc_idp; /* Internal */
358 ushort scc_rbptr; /* Internal */
359 ushort scc_ibc; /* Internal */
360 uint scc_rxtmp; /* Internal */
361 uint scc_tstate; /* Internal */
362 uint scc_tdp; /* Internal */
363 ushort scc_tbptr; /* Internal */
364 ushort scc_tbc; /* Internal */
365 uint scc_txtmp; /* Internal */
366 uint scc_rcrc; /* Internal */
367 uint scc_tcrc; /* Internal */
368} sccp_t;
369
370/* Function code bits.
371*/
372#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
373
374/* CPM Ethernet through SCCx.
375 */
376typedef struct scc_enet {
377 sccp_t sen_genscc;
378 uint sen_cpres; /* Preset CRC */
379 uint sen_cmask; /* Constant mask for CRC */
380 uint sen_crcec; /* CRC Error counter */
381 uint sen_alec; /* alignment error counter */
382 uint sen_disfc; /* discard frame counter */
383 ushort sen_pads; /* Tx short frame pad character */
384 ushort sen_retlim; /* Retry limit threshold */
385 ushort sen_retcnt; /* Retry limit counter */
386 ushort sen_maxflr; /* maximum frame length register */
387 ushort sen_minflr; /* minimum frame length register */
388 ushort sen_maxd1; /* maximum DMA1 length */
389 ushort sen_maxd2; /* maximum DMA2 length */
390 ushort sen_maxd; /* Rx max DMA */
391 ushort sen_dmacnt; /* Rx DMA counter */
392 ushort sen_maxb; /* Max BD byte count */
393 ushort sen_gaddr1; /* Group address filter */
394 ushort sen_gaddr2;
395 ushort sen_gaddr3;
396 ushort sen_gaddr4;
397 uint sen_tbuf0data0; /* Save area 0 - current frame */
398 uint sen_tbuf0data1; /* Save area 1 - current frame */
399 uint sen_tbuf0rba; /* Internal */
400 uint sen_tbuf0crc; /* Internal */
401 ushort sen_tbuf0bcnt; /* Internal */
402 ushort sen_paddrh; /* physical address (MSB) */
403 ushort sen_paddrm;
404 ushort sen_paddrl; /* physical address (LSB) */
405 ushort sen_pper; /* persistence */
406 ushort sen_rfbdptr; /* Rx first BD pointer */
407 ushort sen_tfbdptr; /* Tx first BD pointer */
408 ushort sen_tlbdptr; /* Tx last BD pointer */
409 uint sen_tbuf1data0; /* Save area 0 - current frame */
410 uint sen_tbuf1data1; /* Save area 1 - current frame */
411 uint sen_tbuf1rba; /* Internal */
412 uint sen_tbuf1crc; /* Internal */
413 ushort sen_tbuf1bcnt; /* Internal */
414 ushort sen_txlen; /* Tx Frame length counter */
415 ushort sen_iaddr1; /* Individual address filter */
416 ushort sen_iaddr2;
417 ushort sen_iaddr3;
418 ushort sen_iaddr4;
419 ushort sen_boffcnt; /* Backoff counter */
420
421 /* NOTE: Some versions of the manual have the following items
422 * incorrectly documented. Below is the proper order.
423 */
424 ushort sen_taddrh; /* temp address (MSB) */
425 ushort sen_taddrm;
426 ushort sen_taddrl; /* temp address (LSB) */
427} scc_enet_t;
428
429/**********************************************************************
430 *
431 * Board specific configuration settings.
432 *
433 * Please note that we use the presence of a #define SCC_ENET and/or
434 * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
435 **********************************************************************/
436
437
438/*** ADS *************************************************************/
439
440#if defined(CONFIG_MPC860) && defined(CONFIG_ADS)
441/* This ENET stuff is for the MPC860ADS with ethernet on SCC1.
442 */
443
444#define PROFF_ENET PROFF_SCC1
445#define CPM_CR_ENET CPM_CR_CH_SCC1
446#define SCC_ENET 0
447
448#define PA_ENET_RXD ((ushort)0x0001)
449#define PA_ENET_TXD ((ushort)0x0002)
450#define PA_ENET_TCLK ((ushort)0x0100)
451#define PA_ENET_RCLK ((ushort)0x0200)
452
453#define PB_ENET_TENA ((uint)0x00001000)
454
455#define PC_ENET_CLSN ((ushort)0x0010)
456#define PC_ENET_RENA ((ushort)0x0020)
457
458#define SICR_ENET_MASK ((uint)0x000000ff)
459#define SICR_ENET_CLKRT ((uint)0x0000002c)
460
461/* 68160 PHY control */
462
463#define PC_ENET_ETHLOOP ((ushort)0x0800)
464#define PC_ENET_TPFLDL ((ushort)0x0400)
465#define PC_ENET_TPSQEL ((ushort)0x0200)
466
467#endif /* MPC860ADS */
468
469/*** AMX860 **********************************************/
470
471#if defined(CONFIG_AMX860)
472
473/* This ENET stuff is for the AMX860 with ethernet on SCC1.
474 */
475
476#define PROFF_ENET PROFF_SCC1
477#define CPM_CR_ENET CPM_CR_CH_SCC1
478#define SCC_ENET 0
479
480#define PA_ENET_RXD ((ushort)0x0001)
481#define PA_ENET_TXD ((ushort)0x0002)
482#define PA_ENET_TCLK ((ushort)0x0400)
483#define PA_ENET_RCLK ((ushort)0x0800)
484
485#define PB_ENET_TENA ((uint)0x00001000)
486
487#define PC_ENET_CLSN ((ushort)0x0010)
488#define PC_ENET_RENA ((ushort)0x0020)
489
490#define SICR_ENET_MASK ((uint)0x000000ff)
491#define SICR_ENET_CLKRT ((uint)0x0000003e)
492
493/* 68160 PHY control */
494
495#define PB_ENET_ETHLOOP ((uint)0x00020000)
496#define PB_ENET_TPFLDL ((uint)0x00010000)
497#define PB_ENET_TPSQEL ((uint)0x00008000)
498#define PD_ENET_ETH_EN ((ushort)0x0004)
499
500#endif /* CONFIG_AMX860 */
501
502/*** BSEIP **********************************************************/
503
504#ifdef CONFIG_BSEIP
505/* This ENET stuff is for the MPC823 with ethernet on SCC2.
506 * This is unique to the BSE ip-Engine board.
507 */
508#define PROFF_ENET PROFF_SCC2
509#define CPM_CR_ENET CPM_CR_CH_SCC2
510#define SCC_ENET 1
511#define PA_ENET_RXD ((ushort)0x0004)
512#define PA_ENET_TXD ((ushort)0x0008)
513#define PA_ENET_TCLK ((ushort)0x0100)
514#define PA_ENET_RCLK ((ushort)0x0200)
515#define PB_ENET_TENA ((uint)0x00002000)
516#define PC_ENET_CLSN ((ushort)0x0040)
517#define PC_ENET_RENA ((ushort)0x0080)
518
519/* BSE uses port B and C bits for PHY control also.
520*/
521#define PB_BSE_POWERUP ((uint)0x00000004)
522#define PB_BSE_FDXDIS ((uint)0x00008000)
523#define PC_BSE_LOOPBACK ((ushort)0x0800)
524
525#define SICR_ENET_MASK ((uint)0x0000ff00)
526#define SICR_ENET_CLKRT ((uint)0x00002c00)
527#endif /* CONFIG_BSEIP */
528
529/*** BSEIP **********************************************************/
530
531#ifdef CONFIG_FLAGADM
532/* Enet configuration for the FLAGADM */
533/* Enet on SCC2 */
534
535#define PROFF_ENET PROFF_SCC2
536#define CPM_CR_ENET CPM_CR_CH_SCC2
537#define SCC_ENET 1
wdenk7c7a23b2002-12-07 00:20:59 +0000538#define PA_ENET_RXD ((ushort)0x0004)
539#define PA_ENET_TXD ((ushort)0x0008)
wdenkfe8c2802002-11-03 00:38:21 +0000540#define PA_ENET_TCLK ((ushort)0x0100)
541#define PA_ENET_RCLK ((ushort)0x0400)
542#define PB_ENET_TENA ((uint)0x00002000)
543#define PC_ENET_CLSN ((ushort)0x0040)
544#define PC_ENET_RENA ((ushort)0x0080)
545
546#define SICR_ENET_MASK ((uint)0x0000ff00)
547#define SICR_ENET_CLKRT ((uint)0x00003400)
548#endif /* CONFIG_FLAGADM */
549
550/*** C2MON **********************************************************/
551
552#ifdef CONFIG_C2MON
553
554# ifndef CONFIG_FEC_ENET /* use SCC for 10Mbps Ethernet */
555# error "Ethernet on SCC not supported on C2MON Board!"
556# else /* Use FEC for Fast Ethernet */
557
558#undef SCC_ENET
559#define FEC_ENET
560
561#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
562#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
563#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
564#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
565#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
566#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
567#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
568#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
569#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
570#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
571#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
572#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
573#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
574
575#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
576
577# endif /* CONFIG_FEC_ENET */
578#endif /* CONFIG_C2MON */
579
580/*********************************************************************/
581
wdenk3bac3512003-03-12 10:41:04 +0000582/*** ELPT860 *********************************************************/
583
584#ifdef CONFIG_ELPT860
585/* Bits in parallel I/O port registers that have to be set/cleared
586 * to configure the pins for SCC1 use.
587 */
588# define PROFF_ENET PROFF_SCC1
589# define CPM_CR_ENET CPM_CR_CH_SCC1
590# define SCC_ENET 0
591
592# define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
593# define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
594# define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
595# define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */
596
597# define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
598# define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
599# define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
600
601/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
602 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
603 */
604# define SICR_ENET_MASK ((uint)0x000000FF)
605# define SICR_ENET_CLKRT ((uint)0x00000025)
606#endif /* CONFIG_ELPT860 */
607
wdenkfe8c2802002-11-03 00:38:21 +0000608/*** ESTEEM 192E **************************************************/
609#ifdef CONFIG_ESTEEM192E
610/* ESTEEM192E
611 * This ENET stuff is for the MPC850 with ethernet on SCC2. This
612 * is very similar to the RPX-Lite configuration.
613 * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
614 */
615
616#define PROFF_ENET PROFF_SCC2
617#define CPM_CR_ENET CPM_CR_CH_SCC2
618#define SCC_ENET 1
619
620#define PA_ENET_RXD ((ushort)0x0004)
621#define PA_ENET_TXD ((ushort)0x0008)
622#define PA_ENET_TCLK ((ushort)0x0200)
623#define PA_ENET_RCLK ((ushort)0x0800)
624#define PB_ENET_TENA ((uint)0x00002000)
625#define PC_ENET_CLSN ((ushort)0x0040)
626#define PC_ENET_RENA ((ushort)0x0080)
627
628#define SICR_ENET_MASK ((uint)0x0000ff00)
629#define SICR_ENET_CLKRT ((uint)0x00003d00)
630
631#define PB_ENET_LOOPBACK ((uint)0x00004000)
632#define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
633
634#endif
635
636/*** FADS823 ********************************************************/
637
638#if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS)
639/* This ENET stuff is for the MPC823FADS with ethernet on SCC2.
640 */
641#ifdef CONFIG_SCC2_ENET
642#define PROFF_ENET PROFF_SCC2
643#define CPM_CR_ENET CPM_CR_CH_SCC2
644#define SCC_ENET 1
645#define CPMVEC_ENET CPMVEC_SCC2
646#endif
647
648#ifdef CONFIG_SCC1_ENET
649#define PROFF_ENET PROFF_SCC1
650#define CPM_CR_ENET CPM_CR_CH_SCC1
651#define SCC_ENET 0
652#define CPMVEC_ENET CPMVEC_SCC1
653#endif
654
655#define PA_ENET_RXD ((ushort)0x0004)
656#define PA_ENET_TXD ((ushort)0x0008)
657#define PA_ENET_TCLK ((ushort)0x0400)
658#define PA_ENET_RCLK ((ushort)0x0200)
659
660#define PB_ENET_TENA ((uint)0x00002000)
661
662#define PC_ENET_CLSN ((ushort)0x0040)
663#define PC_ENET_RENA ((ushort)0x0080)
664
665#define SICR_ENET_MASK ((uint)0x0000ff00)
666#define SICR_ENET_CLKRT ((uint)0x00002e00)
667
668#endif /* CONFIG_FADS823FADS */
669
670/*** FADS850SAR ********************************************************/
671
672#if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS)
673/* This ENET stuff is for the MPC850SAR with ethernet on SCC2. Some of
674 * this may be unique to the FADS850SAR configuration.
675 * Note TENA is on Port B.
676 */
677#define PROFF_ENET PROFF_SCC2
678#define CPM_CR_ENET CPM_CR_CH_SCC2
679#define SCC_ENET 1
680#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
681#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
682#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
683#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
684#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
685#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
686#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
687
688#define SICR_ENET_MASK ((uint)0x0000ff00)
689#define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */
690#endif /* CONFIG_FADS850SAR */
691
692/*** FADS860T********************************************************/
693
wdenk180d3f72004-01-04 16:28:35 +0000694#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x)
695/*
696 * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1.
wdenkfe8c2802002-11-03 00:38:21 +0000697 */
wdenkfe8c2802002-11-03 00:38:21 +0000698#ifdef CONFIG_SCC1_ENET
wdenk180d3f72004-01-04 16:28:35 +0000699
wdenkfe8c2802002-11-03 00:38:21 +0000700#define SCC_ENET 0
wdenk180d3f72004-01-04 16:28:35 +0000701
wdenkfe8c2802002-11-03 00:38:21 +0000702#define PROFF_ENET PROFF_SCC1
703#define CPM_CR_ENET CPM_CR_CH_SCC1
704
705#define PA_ENET_RXD ((ushort)0x0001)
706#define PA_ENET_TXD ((ushort)0x0002)
707#define PA_ENET_TCLK ((ushort)0x0100)
708#define PA_ENET_RCLK ((ushort)0x0200)
709
710#define PB_ENET_TENA ((uint)0x00001000)
711
712#define PC_ENET_CLSN ((ushort)0x0010)
713#define PC_ENET_RENA ((ushort)0x0020)
714
715#define SICR_ENET_MASK ((uint)0x000000ff)
716#define SICR_ENET_CLKRT ((uint)0x0000002c)
717
wdenk180d3f72004-01-04 16:28:35 +0000718#endif /* CONFIG_SCC1_ETHERNET */
719
720/*
wdenk11142572004-06-06 21:35:06 +0000721 * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS
722 * with ethernet on FEC.
wdenkfe8c2802002-11-03 00:38:21 +0000723 */
724
725#ifdef CONFIG_FEC_ENET
wdenk180d3f72004-01-04 16:28:35 +0000726#define FEC_ENET /* Use FEC for Ethernet */
727#endif /* CONFIG_FEC_ENET */
wdenkfe8c2802002-11-03 00:38:21 +0000728
wdenk180d3f72004-01-04 16:28:35 +0000729#endif /* CONFIG_FADS && CONFIG_MPC86x */
wdenkfe8c2802002-11-03 00:38:21 +0000730
wdenk384ae022002-11-05 00:17:55 +0000731/*** FPS850L, FPS860L ************************************************/
wdenkfe8c2802002-11-03 00:38:21 +0000732
wdenk384ae022002-11-05 00:17:55 +0000733#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
wdenkfe8c2802002-11-03 00:38:21 +0000734/* Bits in parallel I/O port registers that have to be set/cleared
wdenk384ae022002-11-05 00:17:55 +0000735 * to configure the pins for SCC2 use.
wdenkfe8c2802002-11-03 00:38:21 +0000736 */
737#define PROFF_ENET PROFF_SCC2
738#define CPM_CR_ENET CPM_CR_CH_SCC2
739#define SCC_ENET 1
740#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
741#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
742#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
743#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
744
745#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */
746#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
747#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
748
749/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
750 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
751 */
752#define SICR_ENET_MASK ((uint)0x0000ff00)
753#define SICR_ENET_CLKRT ((uint)0x00002600)
wdenk384ae022002-11-05 00:17:55 +0000754#endif /* CONFIG_FPS850L, CONFIG_FPS860L */
wdenkfe8c2802002-11-03 00:38:21 +0000755
756/*** GEN860T **********************************************************/
757#if defined(CONFIG_GEN860T)
758#undef SCC_ENET
759#define FEC_ENET
760
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200761#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
762#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
763#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
764#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
765#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
766#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
767#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
768#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
769#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
770#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
771#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
772#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
773#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
wdenkfe8c2802002-11-03 00:38:21 +0000774#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */
775#endif /* CONFIG_GEN860T */
776
777/*** GENIETV ********************************************************/
778
779#if defined(CONFIG_GENIETV)
780/* Ethernet is only on SCC2 */
781
782#define CONFIG_SCC2_ENET
783#define PROFF_ENET PROFF_SCC2
784#define CPM_CR_ENET CPM_CR_CH_SCC2
785#define SCC_ENET 1
786#define CPMVEC_ENET CPMVEC_SCC2
787
788#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
789#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
790#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
791#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
792
793#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
794
795#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
796#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
797
798#define SICR_ENET_MASK ((uint)0x0000ff00)
799#define SICR_ENET_CLKRT ((uint)0x00002e00)
800
801#endif /* CONFIG_GENIETV */
802
wdenkfe8c2802002-11-03 00:38:21 +0000803/*** HERMES-PRO ******************************************************/
804
805/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
806
807#ifdef CONFIG_HERMES
808
809#define FEC_ENET /* use FEC for EThernet */
810#undef SCC_ENET
811
812
813#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
814#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
815#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
816#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
817#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
818#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
819#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
820#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
821#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
822#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
823#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
824#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
825#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
826
827#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
828
829#endif /* CONFIG_HERMES */
830
831/*** IAD210 **********************************************************/
832
833/* The IAD210 uses the FEC on a MPC860P for Ethernet */
834
835#if defined(CONFIG_IAD210)
836
837# define FEC_ENET /* use FEC for Ethernet */
838# undef SCC_ENET
839
840# define PD_MII_TXD1 ((ushort) 0x1000 ) /* PD 3 */
841# define PD_MII_TXD2 ((ushort) 0x0800 ) /* PD 4 */
842# define PD_MII_TXD3 ((ushort) 0x0400 ) /* PD 5 */
843# define PD_MII_RX_DV ((ushort) 0x0200 ) /* PD 6 */
844# define PD_MII_RX_ERR ((ushort) 0x0100 ) /* PD 7 */
845# define PD_MII_RX_CLK ((ushort) 0x0080 ) /* PD 8 */
846# define PD_MII_TXD0 ((ushort) 0x0040 ) /* PD 9 */
847# define PD_MII_RXD0 ((ushort) 0x0020 ) /* PD 10 */
848# define PD_MII_TX_ERR ((ushort) 0x0010 ) /* PD 11 */
849# define PD_MII_MDC ((ushort) 0x0008 ) /* PD 12 */
850# define PD_MII_RXD1 ((ushort) 0x0004 ) /* PD 13 */
851# define PD_MII_RXD2 ((ushort) 0x0002 ) /* PD 14 */
852# define PD_MII_RXD3 ((ushort) 0x0001 ) /* PD 15 */
853
854# define PD_MII_MASK ((ushort) 0x1FFF ) /* PD 3...15 */
855
856#endif /* CONFIG_IAD210 */
857
858/*** ICU862 **********************************************************/
859
860#if defined(CONFIG_ICU862)
861
862#ifdef CONFIG_FEC_ENET
863#define FEC_ENET /* use FEC for EThernet */
864#endif /* CONFIG_FEC_ETHERNET */
865
866#endif /* CONFIG_ICU862 */
867
868/*** IP860 **********************************************************/
869
870#if defined(CONFIG_IP860)
871/* Bits in parallel I/O port registers that have to be set/cleared
872 * to configure the pins for SCC1 use.
873 */
874#define PROFF_ENET PROFF_SCC1
875#define CPM_CR_ENET CPM_CR_CH_SCC1
876#define SCC_ENET 0
877#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
878#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
879#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
880#define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */
881
882#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
883#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
884#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
885
886#define PB_ENET_RESET (uint)0x00000008 /* PB 28 */
887#define PB_ENET_JABD (uint)0x00000004 /* PB 29 */
888
889/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
890 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
891 */
892#define SICR_ENET_MASK ((uint)0x000000ff)
893#define SICR_ENET_CLKRT ((uint)0x0000002C)
894#endif /* CONFIG_IP860 */
895
896/*** IVMS8 **********************************************************/
897
898/* The IVMS8 uses the FEC on a MPC860T for Ethernet */
899
900#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
901
902#define FEC_ENET /* use FEC for EThernet */
903#undef SCC_ENET
904
905#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
906
907#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
908
909#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
910#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
911#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
912#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
913#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
914#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
915#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
916#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
917#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
918#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
919#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
920#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
921#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
922
923#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
924
925#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
926
wdenk0608e042004-03-25 19:29:38 +0000927/*** KUP4K, KUP4X ****************************************************/
928/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */
wdenk56f94be2002-11-05 16:35:14 +0000929
wdenk0608e042004-03-25 19:29:38 +0000930#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
wdenk56f94be2002-11-05 16:35:14 +0000931
932#define FEC_ENET /* use FEC for EThernet */
933#undef SCC_ENET
934
935#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
936
937#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
938
939#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
940#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
941#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
942#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
943#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
944#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
945#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
946#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
947#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
948#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
949#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
950#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
951#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
952
953#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
954
955#endif /* CONFIG_KUP4K */
956
957
wdenkfe8c2802002-11-03 00:38:21 +0000958/*** LANTEC *********************************************************/
959
960#if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2
961/* Bits in parallel I/O port registers that have to be set/cleared
962 * to configure the pins for SCC2 use.
963 */
964#define PROFF_ENET PROFF_SCC2
965#define CPM_CR_ENET CPM_CR_CH_SCC2
966#define SCC_ENET 1
967#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
968#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
969#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
970#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
971
972#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
973
974#define PC_ENET_LBK ((ushort)0x0010) /* PC 11 */
975#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
976#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
977
978/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
979 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
980 */
981#define SICR_ENET_MASK ((uint)0x0000FF00)
982#define SICR_ENET_CLKRT ((uint)0x00002E00)
983#endif /* CONFIG_LANTEC v2 */
984
985/*** LWMON **********************************************************/
986
wdenk281e00a2004-08-01 22:48:16 +0000987#if defined(CONFIG_LWMON)
wdenkfe8c2802002-11-03 00:38:21 +0000988/* Bits in parallel I/O port registers that have to be set/cleared
989 * to configure the pins for SCC2 use.
990 */
991#define PROFF_ENET PROFF_SCC2
992#define CPM_CR_ENET CPM_CR_CH_SCC2
993#define SCC_ENET 1
994#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
995#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
996#define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */
997#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
998
999#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1000
1001#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1002#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1003
1004/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
1005 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1006 */
1007#define SICR_ENET_MASK ((uint)0x0000ff00)
1008#define SICR_ENET_CLKRT ((uint)0x00003E00)
1009#endif /* CONFIG_LWMON */
1010
1011/*** NX823 ***********************************************/
1012
1013#if defined(CONFIG_NX823)
1014/* Bits in parallel I/O port registers that have to be set/cleared
1015 * to configure the pins for SCC1 use.
1016 */
1017#define PROFF_ENET PROFF_SCC2
1018#define CPM_CR_ENET CPM_CR_CH_SCC2
1019#define SCC_ENET 1
wdenk7c7a23b2002-12-07 00:20:59 +00001020#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1021#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1022#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1023#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
wdenkfe8c2802002-11-03 00:38:21 +00001024
wdenk7c7a23b2002-12-07 00:20:59 +00001025#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
wdenkfe8c2802002-11-03 00:38:21 +00001026
wdenk7c7a23b2002-12-07 00:20:59 +00001027#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1028#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
wdenkfe8c2802002-11-03 00:38:21 +00001029
1030/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1031 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1032 */
wdenk7c7a23b2002-12-07 00:20:59 +00001033#define SICR_ENET_MASK ((uint)0x0000ff00)
1034#define SICR_ENET_CLKRT ((uint)0x00002f00)
wdenkfe8c2802002-11-03 00:38:21 +00001035
1036#endif /* CONFIG_NX823 */
1037
1038/*** MBX ************************************************************/
1039
1040#ifdef CONFIG_MBX
1041/* Bits in parallel I/O port registers that have to be set/cleared
1042 * to configure the pins for SCC1 use. The TCLK and RCLK seem unique
1043 * to the MBX860 board. Any two of the four available clocks could be
1044 * used, and the MPC860 cookbook manual has an example using different
1045 * clock pins.
1046 */
1047#define PROFF_ENET PROFF_SCC1
1048#define CPM_CR_ENET CPM_CR_CH_SCC1
1049#define SCC_ENET 0
1050#define PA_ENET_RXD ((ushort)0x0001)
1051#define PA_ENET_TXD ((ushort)0x0002)
1052#define PA_ENET_TCLK ((ushort)0x0200)
1053#define PA_ENET_RCLK ((ushort)0x0800)
1054#define PC_ENET_TENA ((ushort)0x0001)
1055#define PC_ENET_CLSN ((ushort)0x0010)
1056#define PC_ENET_RENA ((ushort)0x0020)
1057
1058/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
1059 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1060 */
1061#define SICR_ENET_MASK ((uint)0x000000ff)
1062#define SICR_ENET_CLKRT ((uint)0x0000003d)
1063#endif /* CONFIG_MBX */
1064
Heiko Schocherd0449542009-03-12 07:37:28 +01001065/*** KM8XX *********************************************************/
Heiko Schocher381e4e62008-01-11 01:12:06 +01001066
Heiko Schocherd0449542009-03-12 07:37:28 +01001067/* The KM8XX Service Module uses SCC3 for Ethernet */
Heiko Schocher381e4e62008-01-11 01:12:06 +01001068
Heiko Schocherd0449542009-03-12 07:37:28 +01001069#ifdef CONFIG_KM8XX
Heiko Schocher381e4e62008-01-11 01:12:06 +01001070#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
1071#define CPM_CR_ENET CPM_CR_CH_SCC3
1072#define SCC_ENET 2
1073#define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */
1074#define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */
1075#define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */
1076#define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */
1077
1078#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
1079
1080#define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */
1081#define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */
1082
1083/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to
1084 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
1085 */
1086#define SICR_ENET_MASK ((uint)0x00FF0000)
1087#define SICR_ENET_CLKRT ((uint)0x00250000)
Heiko Schocherd0449542009-03-12 07:37:28 +01001088#endif /* CONFIG_KM8XX */
Heiko Schocher381e4e62008-01-11 01:12:06 +01001089
1090
wdenkfe8c2802002-11-03 00:38:21 +00001091/*** MHPC ********************************************************/
1092
1093#if defined(CONFIG_MHPC)
1094/* This ENET stuff is for the MHPC with ethernet on SCC2.
1095 * Note TENA is on Port B.
1096 */
1097#define PROFF_ENET PROFF_SCC2
1098#define CPM_CR_ENET CPM_CR_CH_SCC2
1099#define SCC_ENET 1
1100#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1101#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1102#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1103#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1104#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1105#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1106#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1107
1108#define SICR_ENET_MASK ((uint)0x0000ff00)
1109#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */
1110#endif /* CONFIG_MHPC */
1111
wdenk608c9142003-01-13 23:54:46 +00001112/*** NETVIA *******************************************************/
1113
wdenkdc7c9a12003-03-26 06:55:25 +00001114/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */
1115#if ( defined CONFIG_SVM_SC8xx )
1116# ifndef CONFIG_FEC_ENET
1117
1118#define PROFF_ENET PROFF_SCC2
1119#define CPM_CR_ENET CPM_CR_CH_SCC2
1120#define SCC_ENET 1
1121
1122 /* Bits in parallel I/O port registers that have to be set/cleared
1123 * * * * to configure the pins for SCC2 use.
1124 * * * */
1125#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1126#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1127#define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */
1128#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
1129
1130#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1131
1132#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1133#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1134/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1135 * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1136 * * * */
1137#define SICR_ENET_MASK ((uint)0x0000ff00)
1138#define SICR_ENET_CLKRT ((uint)0x00003700)
1139
1140# else /* Use FEC for Fast Ethernet */
1141
1142#undef SCC_ENET
1143#define FEC_ENET
1144
1145#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
1146#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
1147#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
1148#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
1149#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
1150#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
1151#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
1152#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
1153#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
1154#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
1155#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
1156#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
1157#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
1158
1159#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
1160
1161# endif /* CONFIG_FEC_ENET */
1162#endif /* CONFIG_SVM_SC8xx */
wdenk8bde7f72003-06-27 21:31:46 +00001163
1164
wdenk608c9142003-01-13 23:54:46 +00001165#if defined(CONFIG_NETVIA)
1166/* Bits in parallel I/O port registers that have to be set/cleared
1167 * to configure the pins for SCC2 use.
1168 */
1169#define PROFF_ENET PROFF_SCC2
1170#define CPM_CR_ENET CPM_CR_CH_SCC2
1171#define SCC_ENET 1
1172#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1173#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1174#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1175#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
1176
wdenk993cad92003-06-26 22:04:09 +00001177#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
1178# define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */
1179#elif CONFIG_NETVIA_VERSION >= 2
1180# define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */
1181#endif
1182
wdenk608c9142003-01-13 23:54:46 +00001183#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */
1184
1185#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1186#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1187
1188/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1189 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1190 */
1191#define SICR_ENET_MASK ((uint)0x0000ff00)
1192#define SICR_ENET_CLKRT ((uint)0x00002f00)
1193
1194#endif /* CONFIG_NETVIA */
1195
wdenk3bbc8992003-12-07 22:27:15 +00001196/*** QS850/QS823 ***************************************************/
1197
1198#if defined(CONFIG_QS850) || defined(CONFIG_QS823)
1199#undef FEC_ENET /* Don't use FEC for EThernet */
1200
1201#define PROFF_ENET PROFF_SCC2
1202#define CPM_CR_ENET CPM_CR_CH_SCC2
1203#define SCC_ENET 1
1204
1205#define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */
1206#define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */
1207#define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */
1208#define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */
1209#define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */
1210#define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */
1211#define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */
1212#define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */
1213#define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */
1214#define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */
1215
1216/* SCC2 TXCLK from CLK2
1217 * SCC2 RXCLK from CLK4
1218 * SCC2 Connected to NMSI */
1219#define SICR_ENET_MASK ((uint)0x00007F00)
1220#define SICR_ENET_CLKRT ((uint)0x00003D00)
1221
1222#endif /* CONFIG_QS850/QS823 */
1223
1224/*** QS860T ***************************************************/
1225
1226#ifdef CONFIG_QS860T
1227#ifdef CONFIG_FEC_ENET
1228#define FEC_ENET /* use FEC for EThernet */
1229#endif /* CONFIG_FEC_ETHERNET */
1230
1231/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
1232#define PROFF_ENET PROFF_SCC1
1233#define CPM_CR_ENET CPM_CR_CH_SCC1
1234#define SCC_ENET 0
1235
1236#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */
1237#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */
1238#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */
1239#define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */
1240#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */
1241#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */
1242#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */
1243
1244#define SICR_ENET_MASK ((uint)0x000000ff)
1245/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */
1246#define SICR_ENET_CLKRT ((uint)0x0000003D)
1247
1248#endif /* CONFIG_QS860T */
1249
wdenkfe8c2802002-11-03 00:38:21 +00001250/*** RPXCLASSIC *****************************************************/
1251
1252#ifdef CONFIG_RPXCLASSIC
1253
1254#ifdef CONFIG_FEC_ENET
1255
1256# define FEC_ENET /* use FEC for EThernet */
1257# undef SCC_ENET
1258
1259#else /* ! CONFIG_FEC_ENET */
1260
1261/* Bits in parallel I/O port registers that have to be set/cleared
1262 * to configure the pins for SCC1 use.
1263 */
1264#define PROFF_ENET PROFF_SCC1
1265#define CPM_CR_ENET CPM_CR_CH_SCC1
1266#define SCC_ENET 0
1267#define PA_ENET_RXD ((ushort)0x0001)
1268#define PA_ENET_TXD ((ushort)0x0002)
1269#define PA_ENET_TCLK ((ushort)0x0200)
1270#define PA_ENET_RCLK ((ushort)0x0800)
1271#define PB_ENET_TENA ((uint)0x00001000)
1272#define PC_ENET_CLSN ((ushort)0x0010)
1273#define PC_ENET_RENA ((ushort)0x0020)
1274
1275/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
1276 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1277 */
1278#define SICR_ENET_MASK ((uint)0x000000ff)
1279#define SICR_ENET_CLKRT ((uint)0x0000003d)
1280
1281#endif /* CONFIG_FEC_ENET */
1282
1283#endif /* CONFIG_RPXCLASSIC */
1284
1285/*** RPXLITE ********************************************************/
1286
1287#ifdef CONFIG_RPXLITE
1288/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
1289 * this may be unique to the RPX-Lite configuration.
1290 * Note TENA is on Port B.
1291 */
1292#define PROFF_ENET PROFF_SCC2
1293#define CPM_CR_ENET CPM_CR_CH_SCC2
1294#define SCC_ENET 1
1295#define PA_ENET_RXD ((ushort)0x0004)
1296#define PA_ENET_TXD ((ushort)0x0008)
1297#define PA_ENET_TCLK ((ushort)0x0200)
1298#define PA_ENET_RCLK ((ushort)0x0800)
wdenk73a8b272003-06-05 19:27:42 +00001299#if defined(CONFIG_RMU)
1300#define PC_ENET_TENA ((uint)0x00000002) /* PC14 */
1301#else
wdenkfe8c2802002-11-03 00:38:21 +00001302#define PB_ENET_TENA ((uint)0x00002000)
wdenk73a8b272003-06-05 19:27:42 +00001303#endif
wdenkfe8c2802002-11-03 00:38:21 +00001304#define PC_ENET_CLSN ((ushort)0x0040)
1305#define PC_ENET_RENA ((ushort)0x0080)
1306
1307#define SICR_ENET_MASK ((uint)0x0000ff00)
1308#define SICR_ENET_CLKRT ((uint)0x00003d00)
1309#endif /* CONFIG_RPXLITE */
1310
1311/*** SM850 *********************************************************/
1312
1313/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
1314
1315#ifdef CONFIG_SM850
1316#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
1317#define CPM_CR_ENET CPM_CR_CH_SCC3
1318#define SCC_ENET 2
1319#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */
1320#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */
1321#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1322#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1323
1324#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
1325#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
1326
1327#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */
1328#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */
1329
1330/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1331 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
1332 */
1333#define SICR_ENET_MASK ((uint)0x00FF0000)
1334#define SICR_ENET_CLKRT ((uint)0x00260000)
1335#endif /* CONFIG_SM850 */
1336
1337/*** SPD823TS ******************************************************/
1338
1339#ifdef CONFIG_SPD823TS
1340/* Bits in parallel I/O port registers that have to be set/cleared
1341 * to configure the pins for SCC2 use.
1342 */
1343#define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */
1344#define CPM_CR_ENET CPM_CR_CH_SCC2
1345#define SCC_ENET 1
1346#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
1347#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
1348#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1349#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1350#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1351#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1352
1353#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1354
1355#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1356#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1357#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
1358
1359/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
1360 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1361 */
1362#define SICR_ENET_MASK ((uint)0x0000ff00)
1363#define SICR_ENET_CLKRT ((uint)0x00002E00)
1364#endif /* CONFIG_SPD823TS */
1365
1366/*** SXNI855T ******************************************************/
1367
1368#if defined(CONFIG_SXNI855T)
1369
1370#ifdef CONFIG_FEC_ENET
1371#define FEC_ENET /* use FEC for Ethernet */
1372#endif /* CONFIG_FEC_ETHERNET */
1373
1374#endif /* CONFIG_SXNI855T */
1375
Markus Klotzbuecher090eb732006-07-12 15:26:01 +02001376/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/
wdenkfe8c2802002-11-03 00:38:21 +00001377
1378#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
wdenk71f95112003-06-15 22:40:42 +00001379 defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
1380 defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
1381 defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +02001382 defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \
1383 defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \
wdenkfe8c2802002-11-03 00:38:21 +00001384 (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +02001385
wdenkfe8c2802002-11-03 00:38:21 +00001386/* Bits in parallel I/O port registers that have to be set/cleared
1387 * to configure the pins for SCC2 use.
1388 */
1389#define PROFF_ENET PROFF_SCC2
1390#define CPM_CR_ENET CPM_CR_CH_SCC2
Wolfgang Denk2b4f7782008-01-15 17:21:28 +01001391#if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */
wdenkfe8c2802002-11-03 00:38:21 +00001392#define SCC_ENET 1
Wolfgang Denk2b4f7782008-01-15 17:21:28 +01001393#endif
wdenkfe8c2802002-11-03 00:38:21 +00001394#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1395#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1396#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1397#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1398
1399#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1400
1401#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1402#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1403#if defined(CONFIG_R360MPI)
1404#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
1405#endif /* CONFIG_R360MPI */
1406
1407/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1408 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1409 */
1410#define SICR_ENET_MASK ((uint)0x0000ff00)
1411#define SICR_ENET_CLKRT ((uint)0x00002600)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +02001412
1413# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
1414#define FEC_ENET
1415# endif /* CONFIG_FEC_ENET */
1416
wdenk71f95112003-06-15 22:40:42 +00001417#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
wdenkfe8c2802002-11-03 00:38:21 +00001418
wdenkd4ca31c2004-01-02 14:00:00 +00001419/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/
wdenkfe8c2802002-11-03 00:38:21 +00001420
wdenk71f95112003-06-15 22:40:42 +00001421#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
1422 defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
wdenkd4ca31c2004-01-02 14:00:00 +00001423 defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
1424 defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
wdenkfe8c2802002-11-03 00:38:21 +00001425
1426# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */
1427
1428/* Bits in parallel I/O port registers that have to be set/cleared
1429 * to configure the pins for SCC1 use.
1430 */
1431#define PROFF_ENET PROFF_SCC1
1432#define CPM_CR_ENET CPM_CR_CH_SCC1
1433#define SCC_ENET 0
1434#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
1435#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
1436#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1437#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1438
1439#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
1440#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
1441#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
1442
1443/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1444 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1445 */
1446#define SICR_ENET_MASK ((uint)0x000000ff)
1447#define SICR_ENET_CLKRT ((uint)0x00000026)
1448
1449# endif /* CONFIG_SCC1_ENET */
1450
1451# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
1452
1453#define FEC_ENET
1454
1455#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
1456#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
1457#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
1458#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
1459#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
1460#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
1461#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
1462#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
1463#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
1464#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
1465#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
1466#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
1467#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
1468
1469#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
1470
1471# endif /* CONFIG_FEC_ENET */
wdenk71f95112003-06-15 22:40:42 +00001472#endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
wdenkfe8c2802002-11-03 00:38:21 +00001473
wdenk608c9142003-01-13 23:54:46 +00001474/*** V37 **********************************************************/
1475
1476#ifdef CONFIG_V37
1477/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of
1478 * this may be unique to the Marel V37 configuration.
1479 * Note TENA is on Port B.
wdenkfe8c2802002-11-03 00:38:21 +00001480 */
1481#define PROFF_ENET PROFF_SCC2
1482#define CPM_CR_ENET CPM_CR_CH_SCC2
1483#define SCC_ENET 1
wdenk608c9142003-01-13 23:54:46 +00001484#define PA_ENET_RXD ((ushort)0x0004)
1485#define PA_ENET_TXD ((ushort)0x0008)
1486#define PA_ENET_TCLK ((ushort)0x0400)
1487#define PA_ENET_RCLK ((ushort)0x0200)
1488#define PB_ENET_TENA ((uint)0x00002000)
1489#define PC_ENET_CLSN ((ushort)0x0040)
1490#define PC_ENET_RENA ((ushort)0x0080)
wdenkfe8c2802002-11-03 00:38:21 +00001491
wdenkfe8c2802002-11-03 00:38:21 +00001492#define SICR_ENET_MASK ((uint)0x0000ff00)
wdenk608c9142003-01-13 23:54:46 +00001493#define SICR_ENET_CLKRT ((uint)0x00002e00)
1494#endif /* CONFIG_V37 */
wdenkfe8c2802002-11-03 00:38:21 +00001495
wdenk3bbc8992003-12-07 22:27:15 +00001496
wdenkfe8c2802002-11-03 00:38:21 +00001497/*********************************************************************/
1498
1499/* SCC Event register as used by Ethernet.
1500*/
1501#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
1502#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
1503#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
1504#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
1505#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
1506#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
1507
1508/* SCC Mode Register (PSMR) as used by Ethernet.
1509*/
1510#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
1511#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
1512#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
1513#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
1514#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
1515#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
1516#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
1517#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
1518#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
1519#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
1520#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
1521#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
1522#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
1523
1524/* Buffer descriptor control/status used by Ethernet receive.
1525*/
1526#define BD_ENET_RX_EMPTY ((ushort)0x8000)
1527#define BD_ENET_RX_WRAP ((ushort)0x2000)
1528#define BD_ENET_RX_INTR ((ushort)0x1000)
1529#define BD_ENET_RX_LAST ((ushort)0x0800)
1530#define BD_ENET_RX_FIRST ((ushort)0x0400)
1531#define BD_ENET_RX_MISS ((ushort)0x0100)
1532#define BD_ENET_RX_LG ((ushort)0x0020)
1533#define BD_ENET_RX_NO ((ushort)0x0010)
1534#define BD_ENET_RX_SH ((ushort)0x0008)
1535#define BD_ENET_RX_CR ((ushort)0x0004)
1536#define BD_ENET_RX_OV ((ushort)0x0002)
1537#define BD_ENET_RX_CL ((ushort)0x0001)
1538#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
1539
1540/* Buffer descriptor control/status used by Ethernet transmit.
1541*/
1542#define BD_ENET_TX_READY ((ushort)0x8000)
1543#define BD_ENET_TX_PAD ((ushort)0x4000)
1544#define BD_ENET_TX_WRAP ((ushort)0x2000)
1545#define BD_ENET_TX_INTR ((ushort)0x1000)
1546#define BD_ENET_TX_LAST ((ushort)0x0800)
1547#define BD_ENET_TX_TC ((ushort)0x0400)
1548#define BD_ENET_TX_DEF ((ushort)0x0200)
1549#define BD_ENET_TX_HB ((ushort)0x0100)
1550#define BD_ENET_TX_LC ((ushort)0x0080)
1551#define BD_ENET_TX_RL ((ushort)0x0040)
1552#define BD_ENET_TX_RCMASK ((ushort)0x003c)
1553#define BD_ENET_TX_UN ((ushort)0x0002)
1554#define BD_ENET_TX_CSL ((ushort)0x0001)
1555#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
1556
1557/* SCC as UART
1558*/
1559typedef struct scc_uart {
1560 sccp_t scc_genscc;
1561 uint scc_res1; /* Reserved */
1562 uint scc_res2; /* Reserved */
1563 ushort scc_maxidl; /* Maximum idle chars */
1564 ushort scc_idlc; /* temp idle counter */
1565 ushort scc_brkcr; /* Break count register */
1566 ushort scc_parec; /* receive parity error counter */
1567 ushort scc_frmec; /* receive framing error counter */
1568 ushort scc_nosec; /* receive noise counter */
1569 ushort scc_brkec; /* receive break condition counter */
1570 ushort scc_brkln; /* last received break length */
1571 ushort scc_uaddr1; /* UART address character 1 */
1572 ushort scc_uaddr2; /* UART address character 2 */
1573 ushort scc_rtemp; /* Temp storage */
1574 ushort scc_toseq; /* Transmit out of sequence char */
1575 ushort scc_char1; /* control character 1 */
1576 ushort scc_char2; /* control character 2 */
1577 ushort scc_char3; /* control character 3 */
1578 ushort scc_char4; /* control character 4 */
1579 ushort scc_char5; /* control character 5 */
1580 ushort scc_char6; /* control character 6 */
1581 ushort scc_char7; /* control character 7 */
1582 ushort scc_char8; /* control character 8 */
1583 ushort scc_rccm; /* receive control character mask */
1584 ushort scc_rccr; /* receive control character register */
1585 ushort scc_rlbc; /* receive last break character */
1586} scc_uart_t;
1587
1588/* SCC Event and Mask registers when it is used as a UART.
1589*/
1590#define UART_SCCM_GLR ((ushort)0x1000)
1591#define UART_SCCM_GLT ((ushort)0x0800)
1592#define UART_SCCM_AB ((ushort)0x0200)
1593#define UART_SCCM_IDL ((ushort)0x0100)
1594#define UART_SCCM_GRA ((ushort)0x0080)
1595#define UART_SCCM_BRKE ((ushort)0x0040)
1596#define UART_SCCM_BRKS ((ushort)0x0020)
1597#define UART_SCCM_CCR ((ushort)0x0008)
1598#define UART_SCCM_BSY ((ushort)0x0004)
1599#define UART_SCCM_TX ((ushort)0x0002)
1600#define UART_SCCM_RX ((ushort)0x0001)
1601
1602/* The SCC PSMR when used as a UART.
1603*/
1604#define SCU_PSMR_FLC ((ushort)0x8000)
1605#define SCU_PSMR_SL ((ushort)0x4000)
1606#define SCU_PSMR_CL ((ushort)0x3000)
1607#define SCU_PSMR_UM ((ushort)0x0c00)
1608#define SCU_PSMR_FRZ ((ushort)0x0200)
1609#define SCU_PSMR_RZS ((ushort)0x0100)
1610#define SCU_PSMR_SYN ((ushort)0x0080)
1611#define SCU_PSMR_DRT ((ushort)0x0040)
1612#define SCU_PSMR_PEN ((ushort)0x0010)
1613#define SCU_PSMR_RPM ((ushort)0x000c)
1614#define SCU_PSMR_REVP ((ushort)0x0008)
1615#define SCU_PSMR_TPM ((ushort)0x0003)
1616#define SCU_PSMR_TEVP ((ushort)0x0003)
1617
1618/* CPM Transparent mode SCC.
1619 */
1620typedef struct scc_trans {
1621 sccp_t st_genscc;
1622 uint st_cpres; /* Preset CRC */
1623 uint st_cmask; /* Constant mask for CRC */
1624} scc_trans_t;
1625
1626#define BD_SCC_TX_LAST ((ushort)0x0800)
1627
1628/* IIC parameter RAM.
1629*/
1630typedef struct iic {
1631 ushort iic_rbase; /* Rx Buffer descriptor base address */
1632 ushort iic_tbase; /* Tx Buffer descriptor base address */
1633 u_char iic_rfcr; /* Rx function code */
1634 u_char iic_tfcr; /* Tx function code */
1635 ushort iic_mrblr; /* Max receive buffer length */
1636 uint iic_rstate; /* Internal */
1637 uint iic_rdp; /* Internal */
1638 ushort iic_rbptr; /* Internal */
1639 ushort iic_rbc; /* Internal */
1640 uint iic_rxtmp; /* Internal */
1641 uint iic_tstate; /* Internal */
1642 uint iic_tdp; /* Internal */
1643 ushort iic_tbptr; /* Internal */
1644 ushort iic_tbc; /* Internal */
1645 uint iic_txtmp; /* Internal */
1646 uint iic_res; /* reserved */
1647 ushort iic_rpbase; /* Relocation pointer */
1648 ushort iic_res2; /* reserved */
1649} iic_t;
1650
1651/* SPI parameter RAM.
1652*/
1653typedef struct spi {
1654 ushort spi_rbase; /* Rx Buffer descriptor base address */
1655 ushort spi_tbase; /* Tx Buffer descriptor base address */
1656 u_char spi_rfcr; /* Rx function code */
1657 u_char spi_tfcr; /* Tx function code */
1658 ushort spi_mrblr; /* Max receive buffer length */
1659 uint spi_rstate; /* Internal */
1660 uint spi_rdp; /* Internal */
1661 ushort spi_rbptr; /* Internal */
1662 ushort spi_rbc; /* Internal */
1663 uint spi_rxtmp; /* Internal */
1664 uint spi_tstate; /* Internal */
1665 uint spi_tdp; /* Internal */
1666 ushort spi_tbptr; /* Internal */
1667 ushort spi_tbc; /* Internal */
1668 uint spi_txtmp; /* Internal */
1669 uint spi_res;
1670 ushort spi_rpbase; /* Relocation pointer */
1671 ushort spi_res2;
1672} spi_t;
1673
1674/* SPI Mode register.
1675*/
1676#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
1677#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
1678#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
1679#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
1680#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
1681#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
1682#define SPMODE_EN ((ushort)0x0100) /* Enable */
1683#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
1684#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
1685
1686#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
1687#define SPMODE_PM(x) ((x) &0xF)
1688
1689/* HDLC parameter RAM.
1690*/
1691
1692typedef struct hdlc_pram_s {
1693 /*
1694 * SCC parameter RAM
1695 */
1696 ushort rbase; /* Rx Buffer descriptor base address */
1697 ushort tbase; /* Tx Buffer descriptor base address */
1698 uchar rfcr; /* Rx function code */
1699 uchar tfcr; /* Tx function code */
1700 ushort mrblr; /* Rx buffer length */
1701 ulong rstate; /* Rx internal state */
1702 ulong rptr; /* Rx internal data pointer */
1703 ushort rbptr; /* rb BD Pointer */
1704 ushort rcount; /* Rx internal byte count */
1705 ulong rtemp; /* Rx temp */
1706 ulong tstate; /* Tx internal state */
1707 ulong tptr; /* Tx internal data pointer */
1708 ushort tbptr; /* Tx BD pointer */
1709 ushort tcount; /* Tx byte count */
1710 ulong ttemp; /* Tx temp */
1711 ulong rcrc; /* temp receive CRC */
1712 ulong tcrc; /* temp transmit CRC */
1713 /*
1714 * HDLC specific parameter RAM
1715 */
1716 uchar res[4]; /* reserved */
1717 ulong c_mask; /* CRC constant */
1718 ulong c_pres; /* CRC preset */
1719 ushort disfc; /* discarded frame counter */
1720 ushort crcec; /* CRC error counter */
1721 ushort abtsc; /* abort sequence counter */
1722 ushort nmarc; /* nonmatching address rx cnt */
1723 ushort retrc; /* frame retransmission cnt */
1724 ushort mflr; /* maximum frame length reg */
1725 ushort max_cnt; /* maximum length counter */
1726 ushort rfthr; /* received frames threshold */
1727 ushort rfcnt; /* received frames count */
1728 ushort hmask; /* user defined frm addr mask */
1729 ushort haddr1; /* user defined frm address 1 */
1730 ushort haddr2; /* user defined frm address 2 */
1731 ushort haddr3; /* user defined frm address 3 */
1732 ushort haddr4; /* user defined frm address 4 */
1733 ushort tmp; /* temp */
1734 ushort tmp_mb; /* temp */
1735} hdlc_pram_t;
1736
1737/* CPM interrupts. There are nearly 32 interrupts generated by CPM
1738 * channels or devices. All of these are presented to the PPC core
1739 * as a single interrupt. The CPM interrupt handler dispatches its
1740 * own handlers, in a similar fashion to the PPC core handler. We
1741 * use the table as defined in the manuals (i.e. no special high
1742 * priority and SCC1 == SCCa, etc...).
1743 */
1744#define CPMVEC_NR 32
wdenk7c7a23b2002-12-07 00:20:59 +00001745#define CPMVEC_OFFSET 0x00010000
1746#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET)
1747#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET)
1748#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET)
1749#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET)
1750#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET)
1751#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET)
1752#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET)
1753#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET)
1754#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET)
1755#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET)
1756#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET)
1757#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET)
1758#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET)
1759#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET)
1760#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET)
1761#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET)
1762#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET)
1763#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET)
1764#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET)
1765#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET)
1766#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET)
1767#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET)
1768#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET)
1769#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET)
1770#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET)
1771#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET)
1772#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET)
1773#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
1774#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
wdenkfe8c2802002-11-03 00:38:21 +00001775
1776extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
1777
1778/* CPM interrupt configuration vector.
1779*/
1780#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
1781#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
1782#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
1783#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
1784#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
1785#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
1786#define CICR_IEN ((uint)0x00000080) /* Int. enable */
1787#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
1788#endif /* __CPM_8XX__ */