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Michal Simek1d6c54e2018-04-12 17:39:46 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
4 */
5
6#include <common.h>
Simon Glass9a3b4ce2019-12-28 10:45:01 -07007#include <cpu_func.h>
Simon Glass691d7192020-05-10 11:40:02 -06008#include <init.h>
Michal Simek1d6c54e2018-04-12 17:39:46 +02009#include <asm/armv7_mpu.h>
Simon Glass401d1c42020-10-30 21:38:53 -060010#include <asm/global_data.h>
Michal Simek1d6c54e2018-04-12 17:39:46 +020011
12DECLARE_GLOBAL_DATA_PTR;
13
14struct mpu_region_config region_config[] = {
Michal Simeke3259a72020-09-14 16:33:46 +020015 { 0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW,
16 SHARED_WRITE_BUFFERED, REGION_4GB },
17 { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
Michal Simek1d6c54e2018-04-12 17:39:46 +020018 O_I_WB_RD_WR_ALLOC, REGION_1GB },
19};
20
21int arch_cpu_init(void)
22{
23 gd->cpu_clk = CONFIG_CPU_FREQ_HZ;
24
Michal Simeke3259a72020-09-14 16:33:46 +020025 setup_mpu_regions(region_config, ARRAY_SIZE(region_config));
Michal Simek1d6c54e2018-04-12 17:39:46 +020026
27 return 0;
28}
29
30/*
31 * Perform the low-level reset.
32 */
Harald Seiler35b65dd2020-12-15 16:47:52 +010033void reset_cpu(void)
Michal Simek1d6c54e2018-04-12 17:39:46 +020034{
35 while (1)
36 ;
37}