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Michal Simekcf0bcd72018-03-28 15:43:51 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU106
4 *
Michal Simek447fb8d2021-05-31 09:50:01 +02005 * (C) Copyright 2016 - 2021, Xilinx, Inc.
Michal Simekcf0bcd72018-03-28 15:43:51 +02006 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
Michal Simekbd008492021-05-10 13:14:02 +020016#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
Michal Simekcf0bcd72018-03-28 15:43:51 +020017#include <dt-bindings/phy/phy.h>
18
19/ {
20 model = "ZynqMP ZCU106 RevA";
21 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
22
23 aliases {
24 ethernet0 = &gem3;
Michal Simekcf0bcd72018-03-28 15:43:51 +020025 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 mmc0 = &sdhci1;
Michal Simek531abcb2021-06-03 11:46:50 +020028 nvmem0 = &eeprom;
Michal Simekcf0bcd72018-03-28 15:43:51 +020029 rtc0 = &rtc;
30 serial0 = &uart0;
31 serial1 = &uart1;
32 serial2 = &dcc;
33 spi0 = &qspi;
34 usb0 = &usb0;
35 };
36
37 chosen {
38 bootargs = "earlycon";
39 stdout-path = "serial0:115200n8";
40 };
41
42 memory@0 {
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
45 };
46
47 gpio-keys {
48 compatible = "gpio-keys";
Michal Simekcf0bcd72018-03-28 15:43:51 +020049 autorepeat;
50 sw19 {
51 label = "sw19";
52 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
53 linux,code = <KEY_DOWN>;
Sudeep Hollaad967af2018-10-24 12:45:40 +010054 wakeup-source;
Michal Simekcf0bcd72018-03-28 15:43:51 +020055 autorepeat;
56 };
57 };
58
59 leds {
60 compatible = "gpio-leds";
Michal Simek096d7f52018-11-08 10:06:53 +010061 heartbeat-led {
Michal Simekcf0bcd72018-03-28 15:43:51 +020062 label = "heartbeat";
63 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
64 linux,default-trigger = "heartbeat";
65 };
66 };
Michal Simek777c4d62019-08-26 09:46:36 +020067
68 ina226-u76 {
69 compatible = "iio-hwmon";
70 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
71 };
72 ina226-u77 {
73 compatible = "iio-hwmon";
74 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
75 };
76 ina226-u78 {
77 compatible = "iio-hwmon";
78 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
79 };
80 ina226-u87 {
81 compatible = "iio-hwmon";
82 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
83 };
84 ina226-u85 {
85 compatible = "iio-hwmon";
86 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
87 };
88 ina226-u86 {
89 compatible = "iio-hwmon";
90 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
91 };
92 ina226-u93 {
93 compatible = "iio-hwmon";
94 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
95 };
96 ina226-u88 {
97 compatible = "iio-hwmon";
98 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
99 };
100 ina226-u15 {
101 compatible = "iio-hwmon";
102 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
103 };
104 ina226-u92 {
105 compatible = "iio-hwmon";
106 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
107 };
108 ina226-u79 {
109 compatible = "iio-hwmon";
110 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
111 };
112 ina226-u81 {
113 compatible = "iio-hwmon";
114 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
115 };
116 ina226-u80 {
117 compatible = "iio-hwmon";
118 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
119 };
120 ina226-u84 {
121 compatible = "iio-hwmon";
122 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
123 };
124 ina226-u16 {
125 compatible = "iio-hwmon";
126 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
127 };
128 ina226-u65 {
129 compatible = "iio-hwmon";
130 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
131 };
132 ina226-u74 {
133 compatible = "iio-hwmon";
134 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
135 };
136 ina226-u75 {
137 compatible = "iio-hwmon";
138 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
139 };
Michal Simekce906542020-11-26 14:25:02 +0100140
141 /* 48MHz reference crystal */
142 ref48: ref48M {
143 compatible = "fixed-clock";
144 #clock-cells = <0>;
145 clock-frequency = <48000000>;
146 };
147
148 refhdmi: refhdmi {
149 compatible = "fixed-clock";
150 #clock-cells = <0>;
151 clock-frequency = <114285000>;
152 };
Michal Simekcf0bcd72018-03-28 15:43:51 +0200153};
154
155&can1 {
156 status = "okay";
Michal Simekbd008492021-05-10 13:14:02 +0200157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_can1_default>;
Michal Simekcf0bcd72018-03-28 15:43:51 +0200159};
160
161&dcc {
162 status = "okay";
163};
164
165&fpd_dma_chan1 {
166 status = "okay";
167};
168
169&fpd_dma_chan2 {
170 status = "okay";
171};
172
173&fpd_dma_chan3 {
174 status = "okay";
175};
176
177&fpd_dma_chan4 {
178 status = "okay";
179};
180
181&fpd_dma_chan5 {
182 status = "okay";
183};
184
185&fpd_dma_chan6 {
186 status = "okay";
187};
188
189&fpd_dma_chan7 {
190 status = "okay";
191};
192
193&fpd_dma_chan8 {
194 status = "okay";
195};
196
197&gem3 {
198 status = "okay";
199 phy-handle = <&phy0>;
200 phy-mode = "rgmii-id";
Michal Simekbd008492021-05-10 13:14:02 +0200201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_gem3_default>;
Michal Simek2975a422019-08-08 12:44:22 +0200203 phy0: ethernet-phy@c {
Michal Simekcf0bcd72018-03-28 15:43:51 +0200204 reg = <0xc>;
205 ti,rx-internal-delay = <0x8>;
206 ti,tx-internal-delay = <0xa>;
207 ti,fifo-depth = <0x1>;
Harini Katakam631d9a92019-02-13 17:02:21 +0530208 ti,dp83867-rxctrl-strap-quirk;
Michal Simekcf0bcd72018-03-28 15:43:51 +0200209 };
210};
211
212&gpio {
213 status = "okay";
Michal Simekbd008492021-05-10 13:14:02 +0200214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_gpio_default>;
Michal Simekcf0bcd72018-03-28 15:43:51 +0200216};
217
218&gpu {
219 status = "okay";
220};
221
222&i2c0 {
223 status = "okay";
224 clock-frequency = <400000>;
Michal Simekbd008492021-05-10 13:14:02 +0200225 pinctrl-names = "default", "gpio";
226 pinctrl-0 = <&pinctrl_i2c0_default>;
227 pinctrl-1 = <&pinctrl_i2c0_gpio>;
228 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
229 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
Michal Simekcf0bcd72018-03-28 15:43:51 +0200230
231 tca6416_u97: gpio@20 {
232 compatible = "ti,tca6416";
233 reg = <0x20>;
234 gpio-controller; /* interrupt not connected */
235 #gpio-cells = <2>;
236 /*
237 * IRQ not connected
238 * Lines:
239 * 0 - SFP_SI5328_INT_ALM
240 * 1 - HDMI_SI5328_INT_ALM
241 * 5 - IIC_MUX_RESET_B
242 * 6 - GEM3_EXP_RESET_B
243 * 10 - FMC_HPC0_PRSNT_M2C_B
244 * 11 - FMC_HPC1_PRSNT_M2C_B
245 * 2-4, 7, 12-17 - not connected
246 */
247 };
248
249 tca6416_u61: gpio@21 {
250 compatible = "ti,tca6416";
251 reg = <0x21>;
252 gpio-controller;
253 #gpio-cells = <2>;
254 /*
255 * IRQ not connected
256 * Lines:
257 * 0 - VCCPSPLL_EN
258 * 1 - MGTRAVCC_EN
259 * 2 - MGTRAVTT_EN
260 * 3 - VCCPSDDRPLL_EN
261 * 4 - MIO26_PMU_INPUT_LS
262 * 5 - PL_PMBUS_ALERT
263 * 6 - PS_PMBUS_ALERT
264 * 7 - MAXIM_PMBUS_ALERT
265 * 10 - PL_DDR4_VTERM_EN
266 * 11 - PL_DDR4_VPP_2V5_EN
267 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
268 * 13 - PS_DIMM_SUSPEND_EN
269 * 14 - PS_DDR4_VTERM_EN
270 * 15 - PS_DDR4_VPP_2V5_EN
271 * 16 - 17 - not connected
272 */
273 };
274
275 i2c-mux@75 { /* u60 */
276 compatible = "nxp,pca9544";
277 #address-cells = <1>;
278 #size-cells = <0>;
279 reg = <0x75>;
280 i2c@0 {
281 #address-cells = <1>;
282 #size-cells = <0>;
283 reg = <0>;
284 /* PS_PMBUS */
Michal Simek777c4d62019-08-26 09:46:36 +0200285 u76: ina226@40 { /* u76 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200286 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200287 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200288 label = "ina226-u76";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200289 reg = <0x40>;
290 shunt-resistor = <5000>;
291 };
Michal Simek777c4d62019-08-26 09:46:36 +0200292 u77: ina226@41 { /* u77 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200293 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200294 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200295 label = "ina226-u77";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200296 reg = <0x41>;
297 shunt-resistor = <5000>;
298 };
Michal Simek777c4d62019-08-26 09:46:36 +0200299 u78: ina226@42 { /* u78 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200300 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200301 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200302 label = "ina226-u78";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200303 reg = <0x42>;
304 shunt-resistor = <5000>;
305 };
Michal Simek777c4d62019-08-26 09:46:36 +0200306 u87: ina226@43 { /* u87 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200307 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200308 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200309 label = "ina226-u87";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200310 reg = <0x43>;
311 shunt-resistor = <5000>;
312 };
Michal Simek777c4d62019-08-26 09:46:36 +0200313 u85: ina226@44 { /* u85 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200314 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200315 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200316 label = "ina226-u85";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200317 reg = <0x44>;
318 shunt-resistor = <5000>;
319 };
Michal Simek777c4d62019-08-26 09:46:36 +0200320 u86: ina226@45 { /* u86 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200321 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200322 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200323 label = "ina226-u86";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200324 reg = <0x45>;
325 shunt-resistor = <5000>;
326 };
Michal Simek777c4d62019-08-26 09:46:36 +0200327 u93: ina226@46 { /* u93 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200328 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200329 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200330 label = "ina226-u93";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200331 reg = <0x46>;
332 shunt-resistor = <5000>;
333 };
Michal Simek777c4d62019-08-26 09:46:36 +0200334 u88: ina226@47 { /* u88 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200335 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200336 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200337 label = "ina226-u88";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200338 reg = <0x47>;
339 shunt-resistor = <5000>;
340 };
Michal Simek777c4d62019-08-26 09:46:36 +0200341 u15: ina226@4a { /* u15 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200342 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200343 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200344 label = "ina226-u15";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200345 reg = <0x4a>;
346 shunt-resistor = <5000>;
347 };
Michal Simek777c4d62019-08-26 09:46:36 +0200348 u92: ina226@4b { /* u92 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200349 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200350 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200351 label = "ina226-u92";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200352 reg = <0x4b>;
353 shunt-resistor = <5000>;
354 };
355 };
356 i2c@1 {
357 #address-cells = <1>;
358 #size-cells = <0>;
359 reg = <1>;
360 /* PL_PMBUS */
Michal Simek777c4d62019-08-26 09:46:36 +0200361 u79: ina226@40 { /* u79 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200362 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200363 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200364 label = "ina226-u79";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200365 reg = <0x40>;
366 shunt-resistor = <2000>;
367 };
Michal Simek777c4d62019-08-26 09:46:36 +0200368 u81: ina226@41 { /* u81 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200369 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200370 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200371 label = "ina226-u81";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200372 reg = <0x41>;
373 shunt-resistor = <5000>;
374 };
Michal Simek777c4d62019-08-26 09:46:36 +0200375 u80: ina226@42 { /* u80 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200376 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200377 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200378 label = "ina226-u80";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200379 reg = <0x42>;
380 shunt-resistor = <5000>;
381 };
Michal Simek777c4d62019-08-26 09:46:36 +0200382 u84: ina226@43 { /* u84 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200383 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200384 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200385 label = "ina226-u84";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200386 reg = <0x43>;
387 shunt-resistor = <5000>;
388 };
Michal Simek777c4d62019-08-26 09:46:36 +0200389 u16: ina226@44 { /* u16 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200390 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200391 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200392 label = "ina226-u16";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200393 reg = <0x44>;
394 shunt-resistor = <5000>;
395 };
Michal Simek777c4d62019-08-26 09:46:36 +0200396 u65: ina226@45 { /* u65 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200397 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200398 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200399 label = "ina226-u65";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200400 reg = <0x45>;
401 shunt-resistor = <5000>;
402 };
Michal Simek777c4d62019-08-26 09:46:36 +0200403 u74: ina226@46 { /* u74 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200404 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200405 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200406 label = "ina226-u74";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200407 reg = <0x46>;
408 shunt-resistor = <5000>;
409 };
Michal Simek777c4d62019-08-26 09:46:36 +0200410 u75: ina226@47 { /* u75 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200411 compatible = "ti,ina226";
Michal Simek777c4d62019-08-26 09:46:36 +0200412 #io-channel-cells = <1>;
Michal Simek5c097092019-08-26 10:18:13 +0200413 label = "ina226-u75";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200414 reg = <0x47>;
415 shunt-resistor = <5000>;
416 };
417 };
418 i2c@2 {
419 #address-cells = <1>;
420 #size-cells = <0>;
421 reg = <2>;
422 /* MAXIM_PMBUS - 00 */
423 max15301@a { /* u46 */
424 compatible = "maxim,max15301";
425 reg = <0xa>;
426 };
427 max15303@b { /* u4 */
428 compatible = "maxim,max15303";
429 reg = <0xb>;
430 };
431 max15303@10 { /* u13 */
432 compatible = "maxim,max15303";
433 reg = <0x10>;
434 };
435 max15301@13 { /* u47 */
436 compatible = "maxim,max15301";
437 reg = <0x13>;
438 };
439 max15303@14 { /* u7 */
440 compatible = "maxim,max15303";
441 reg = <0x14>;
442 };
443 max15303@15 { /* u6 */
444 compatible = "maxim,max15303";
445 reg = <0x15>;
446 };
447 max15303@16 { /* u10 */
448 compatible = "maxim,max15303";
449 reg = <0x16>;
450 };
451 max15303@17 { /* u9 */
452 compatible = "maxim,max15303";
453 reg = <0x17>;
454 };
455 max15301@18 { /* u63 */
456 compatible = "maxim,max15301";
457 reg = <0x18>;
458 };
459 max15303@1a { /* u49 */
460 compatible = "maxim,max15303";
461 reg = <0x1a>;
462 };
463 max15303@1b { /* u8 */
464 compatible = "maxim,max15303";
465 reg = <0x1b>;
466 };
467 max15303@1d { /* u18 */
468 compatible = "maxim,max15303";
469 reg = <0x1d>;
470 };
471
472 max20751@72 { /* u95 */
473 compatible = "maxim,max20751";
474 reg = <0x72>;
475 };
476 max20751@73 { /* u96 */
477 compatible = "maxim,max20751";
478 reg = <0x73>;
479 };
480 };
481 /* Bus 3 is not connected */
482 };
483};
484
485&i2c1 {
486 status = "okay";
487 clock-frequency = <400000>;
Michal Simekbd008492021-05-10 13:14:02 +0200488 pinctrl-names = "default", "gpio";
489 pinctrl-0 = <&pinctrl_i2c1_default>;
490 pinctrl-1 = <&pinctrl_i2c1_gpio>;
491 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
492 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
Michal Simekcf0bcd72018-03-28 15:43:51 +0200493
494 /* PL i2c via PCA9306 - u45 */
495 i2c-mux@74 { /* u34 */
496 compatible = "nxp,pca9548";
497 #address-cells = <1>;
498 #size-cells = <0>;
499 reg = <0x74>;
500 i2c@0 {
501 #address-cells = <1>;
502 #size-cells = <0>;
503 reg = <0>;
504 /*
505 * IIC_EEPROM 1kB memory which uses 256B blocks
506 * where every block has different address.
507 * 0 - 256B address 0x54
508 * 256B - 512B address 0x55
509 * 512B - 768B address 0x56
510 * 768B - 1024B address 0x57
511 */
512 eeprom: eeprom@54 { /* u23 */
513 compatible = "atmel,24c08";
514 reg = <0x54>;
515 };
516 };
517 i2c@1 {
518 #address-cells = <1>;
519 #size-cells = <0>;
520 reg = <1>;
521 si5341: clock-generator@36 { /* SI5341 - u69 */
Michal Simekce906542020-11-26 14:25:02 +0100522 compatible = "silabs,si5341";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200523 reg = <0x36>;
Michal Simekce906542020-11-26 14:25:02 +0100524 #clock-cells = <2>;
525 #address-cells = <1>;
526 #size-cells = <0>;
527 clocks = <&ref48>;
528 clock-names = "xtal";
529 clock-output-names = "si5341";
530
531 si5341_0: out@0 {
532 /* refclk0 for PS-GT, used for DP */
533 reg = <0>;
534 always-on;
535 };
536 si5341_2: out@2 {
537 /* refclk2 for PS-GT, used for USB3 */
538 reg = <2>;
539 always-on;
540 };
541 si5341_3: out@3 {
542 /* refclk3 for PS-GT, used for SATA */
543 reg = <3>;
544 always-on;
545 };
546 si5341_6: out@6 {
547 /* refclk6 PL CLK125 */
548 reg = <6>;
549 always-on;
550 };
551 si5341_7: out@7 {
552 /* refclk7 PL CLK74 */
553 reg = <7>;
554 always-on;
555 };
556 si5341_9: out@9 {
557 /* refclk9 used for PS_REF_CLK 33.3 MHz */
558 reg = <9>;
559 always-on;
560 };
Michal Simekcf0bcd72018-03-28 15:43:51 +0200561 };
562
563 };
564 i2c@2 {
565 #address-cells = <1>;
566 #size-cells = <0>;
567 reg = <2>;
568 si570_1: clock-generator@5d { /* USER SI570 - u42 */
569 #clock-cells = <0>;
570 compatible = "silabs,si570";
571 reg = <0x5d>;
572 temperature-stability = <50>;
573 factory-fout = <300000000>;
574 clock-frequency = <300000000>;
Michal Simek6bd13ee2018-07-18 12:10:02 +0200575 clock-output-names = "si570_user";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200576 };
577 };
578 i2c@3 {
579 #address-cells = <1>;
580 #size-cells = <0>;
581 reg = <3>;
582 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
583 #clock-cells = <0>;
584 compatible = "silabs,si570";
585 reg = <0x5d>;
586 temperature-stability = <50>; /* copy from zc702 */
587 factory-fout = <156250000>;
588 clock-frequency = <148500000>;
Michal Simek6bd13ee2018-07-18 12:10:02 +0200589 clock-output-names = "si570_mgt";
Michal Simekcf0bcd72018-03-28 15:43:51 +0200590 };
591 };
592 i2c@4 {
593 #address-cells = <1>;
594 #size-cells = <0>;
595 reg = <4>;
Michal Simek43086882021-06-03 11:58:08 +0200596 /* SI5328 - u20 */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200597 };
598 i2c@5 {
599 #address-cells = <1>;
600 #size-cells = <0>;
601 reg = <5>; /* FAN controller */
602 temp@4c {/* lm96163 - u128 */
603 compatible = "national,lm96163";
604 reg = <0x4c>;
605 };
606 };
607 /* 6 - 7 unconnected */
608 };
609
610 i2c-mux@75 {
611 compatible = "nxp,pca9548"; /* u135 */
612 #address-cells = <1>;
613 #size-cells = <0>;
614 reg = <0x75>;
615
616 i2c@0 {
617 #address-cells = <1>;
618 #size-cells = <0>;
619 reg = <0>;
620 /* HPC0_IIC */
621 };
622 i2c@1 {
623 #address-cells = <1>;
624 #size-cells = <0>;
625 reg = <1>;
626 /* HPC1_IIC */
627 };
628 i2c@2 {
629 #address-cells = <1>;
630 #size-cells = <0>;
631 reg = <2>;
632 /* SYSMON */
633 };
634 i2c@3 {
635 #address-cells = <1>;
636 #size-cells = <0>;
637 reg = <3>;
638 /* DDR4 SODIMM */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200639 };
640 i2c@4 {
641 #address-cells = <1>;
642 #size-cells = <0>;
643 reg = <4>;
644 /* SEP 3 */
645 };
646 i2c@5 {
647 #address-cells = <1>;
648 #size-cells = <0>;
649 reg = <5>;
650 /* SEP 2 */
651 };
652 i2c@6 {
653 #address-cells = <1>;
654 #size-cells = <0>;
655 reg = <6>;
656 /* SEP 1 */
657 };
658 i2c@7 {
659 #address-cells = <1>;
660 #size-cells = <0>;
661 reg = <7>;
662 /* SEP 0 */
663 };
664 };
665};
666
Michal Simekbd008492021-05-10 13:14:02 +0200667&pinctrl0 {
668 status = "okay";
669 pinctrl_i2c0_default: i2c0-default {
670 mux {
671 groups = "i2c0_3_grp";
672 function = "i2c0";
673 };
674
675 conf {
676 groups = "i2c0_3_grp";
677 bias-pull-up;
678 slew-rate = <SLEW_RATE_SLOW>;
679 power-source = <IO_STANDARD_LVCMOS18>;
680 };
681 };
682
683 pinctrl_i2c0_gpio: i2c0-gpio {
684 mux {
685 groups = "gpio0_14_grp", "gpio0_15_grp";
686 function = "gpio0";
687 };
688
689 conf {
690 groups = "gpio0_14_grp", "gpio0_15_grp";
691 slew-rate = <SLEW_RATE_SLOW>;
692 power-source = <IO_STANDARD_LVCMOS18>;
693 };
694 };
695
696 pinctrl_i2c1_default: i2c1-default {
697 mux {
698 groups = "i2c1_4_grp";
699 function = "i2c1";
700 };
701
702 conf {
703 groups = "i2c1_4_grp";
704 bias-pull-up;
705 slew-rate = <SLEW_RATE_SLOW>;
706 power-source = <IO_STANDARD_LVCMOS18>;
707 };
708 };
709
710 pinctrl_i2c1_gpio: i2c1-gpio {
711 mux {
712 groups = "gpio0_16_grp", "gpio0_17_grp";
713 function = "gpio0";
714 };
715
716 conf {
717 groups = "gpio0_16_grp", "gpio0_17_grp";
718 slew-rate = <SLEW_RATE_SLOW>;
719 power-source = <IO_STANDARD_LVCMOS18>;
720 };
721 };
722
723 pinctrl_uart0_default: uart0-default {
724 mux {
725 groups = "uart0_4_grp";
726 function = "uart0";
727 };
728
729 conf {
730 groups = "uart0_4_grp";
731 slew-rate = <SLEW_RATE_SLOW>;
732 power-source = <IO_STANDARD_LVCMOS18>;
733 };
734
735 conf-rx {
736 pins = "MIO18";
737 bias-high-impedance;
738 };
739
740 conf-tx {
741 pins = "MIO19";
742 bias-disable;
743 };
744 };
745
746 pinctrl_uart1_default: uart1-default {
747 mux {
748 groups = "uart1_5_grp";
749 function = "uart1";
750 };
751
752 conf {
753 groups = "uart1_5_grp";
754 slew-rate = <SLEW_RATE_SLOW>;
755 power-source = <IO_STANDARD_LVCMOS18>;
756 };
757
758 conf-rx {
759 pins = "MIO21";
760 bias-high-impedance;
761 };
762
763 conf-tx {
764 pins = "MIO20";
765 bias-disable;
766 };
767 };
768
769 pinctrl_usb0_default: usb0-default {
770 mux {
771 groups = "usb0_0_grp";
772 function = "usb0";
773 };
774
775 conf {
776 groups = "usb0_0_grp";
777 slew-rate = <SLEW_RATE_SLOW>;
778 power-source = <IO_STANDARD_LVCMOS18>;
779 };
780
781 conf-rx {
782 pins = "MIO52", "MIO53", "MIO55";
783 bias-high-impedance;
784 };
785
786 conf-tx {
787 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
788 "MIO60", "MIO61", "MIO62", "MIO63";
789 bias-disable;
790 };
791 };
792
793 pinctrl_gem3_default: gem3-default {
794 mux {
795 function = "ethernet3";
796 groups = "ethernet3_0_grp";
797 };
798
799 conf {
800 groups = "ethernet3_0_grp";
801 slew-rate = <SLEW_RATE_SLOW>;
802 power-source = <IO_STANDARD_LVCMOS18>;
803 };
804
805 conf-rx {
806 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
807 "MIO75";
808 bias-high-impedance;
809 low-power-disable;
810 };
811
812 conf-tx {
813 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
814 "MIO69";
815 bias-disable;
816 low-power-enable;
817 };
818
819 mux-mdio {
820 function = "mdio3";
821 groups = "mdio3_0_grp";
822 };
823
824 conf-mdio {
825 groups = "mdio3_0_grp";
826 slew-rate = <SLEW_RATE_SLOW>;
827 power-source = <IO_STANDARD_LVCMOS18>;
828 bias-disable;
829 };
830 };
831
832 pinctrl_can1_default: can1-default {
833 mux {
834 function = "can1";
835 groups = "can1_6_grp";
836 };
837
838 conf {
839 groups = "can1_6_grp";
840 slew-rate = <SLEW_RATE_SLOW>;
841 power-source = <IO_STANDARD_LVCMOS18>;
842 };
843
844 conf-rx {
845 pins = "MIO25";
846 bias-high-impedance;
847 };
848
849 conf-tx {
850 pins = "MIO24";
851 bias-disable;
852 };
853 };
854
855 pinctrl_sdhci1_default: sdhci1-default {
856 mux {
857 groups = "sdio1_0_grp";
858 function = "sdio1";
859 };
860
861 conf {
862 groups = "sdio1_0_grp";
863 slew-rate = <SLEW_RATE_SLOW>;
864 power-source = <IO_STANDARD_LVCMOS18>;
865 bias-disable;
866 };
867
868 mux-cd {
869 groups = "sdio1_cd_0_grp";
870 function = "sdio1_cd";
871 };
872
873 conf-cd {
874 groups = "sdio1_cd_0_grp";
875 bias-high-impedance;
876 bias-pull-up;
877 slew-rate = <SLEW_RATE_SLOW>;
878 power-source = <IO_STANDARD_LVCMOS18>;
879 };
880
881 mux-wp {
882 groups = "sdio1_wp_0_grp";
883 function = "sdio1_wp";
884 };
885
886 conf-wp {
887 groups = "sdio1_wp_0_grp";
888 bias-high-impedance;
889 bias-pull-up;
890 slew-rate = <SLEW_RATE_SLOW>;
891 power-source = <IO_STANDARD_LVCMOS18>;
892 };
893 };
894
895 pinctrl_gpio_default: gpio-default {
896 mux {
897 function = "gpio0";
898 groups = "gpio0_22_grp", "gpio0_23_grp";
899 };
900
901 conf {
902 groups = "gpio0_22_grp", "gpio0_23_grp";
903 slew-rate = <SLEW_RATE_SLOW>;
904 power-source = <IO_STANDARD_LVCMOS18>;
905 };
906
907 mux-msp {
908 function = "gpio0";
909 groups = "gpio0_13_grp", "gpio0_38_grp";
910 };
911
912 conf-msp {
913 groups = "gpio0_13_grp", "gpio0_38_grp";
914 slew-rate = <SLEW_RATE_SLOW>;
915 power-source = <IO_STANDARD_LVCMOS18>;
916 };
917
918 conf-pull-up {
919 pins = "MIO22";
920 bias-pull-up;
921 };
922
923 conf-pull-none {
924 pins = "MIO13", "MIO23", "MIO38";
925 bias-disable;
926 };
927 };
928};
929
Michal Simek5fa96722021-06-01 16:42:50 +0200930&psgtr {
931 status = "okay";
932 /* nc, sata, usb3, dp */
933 clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
934 clock-names = "ref1", "ref2", "ref3";
935};
936
Michal Simekcf0bcd72018-03-28 15:43:51 +0200937&qspi {
938 status = "okay";
939 is-dual = <1>;
940 flash@0 {
Neil Armstrongffd4c7c2019-02-10 10:16:20 +0000941 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200942 #address-cells = <1>;
943 #size-cells = <1>;
944 reg = <0x0>;
945 spi-tx-bus-width = <1>;
946 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
947 spi-max-frequency = <108000000>; /* Based on DC1 spec */
Michal Simek5df63a62020-02-14 14:19:56 +0100948 partition@0 { /* for testing purpose */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200949 label = "qspi-fsbl-uboot";
950 reg = <0x0 0x100000>;
951 };
Michal Simek5df63a62020-02-14 14:19:56 +0100952 partition@100000 { /* for testing purpose */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200953 label = "qspi-linux";
954 reg = <0x100000 0x500000>;
955 };
Michal Simek5df63a62020-02-14 14:19:56 +0100956 partition@600000 { /* for testing purpose */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200957 label = "qspi-device-tree";
958 reg = <0x600000 0x20000>;
959 };
Michal Simek5df63a62020-02-14 14:19:56 +0100960 partition@620000 { /* for testing purpose */
Michal Simekcf0bcd72018-03-28 15:43:51 +0200961 label = "qspi-rootfs";
962 reg = <0x620000 0x5E0000>;
963 };
964 };
965};
966
967&rtc {
968 status = "okay";
969};
970
971&sata {
972 status = "okay";
973 /* SATA OOB timing settings */
974 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
975 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
976 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
977 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
978 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
979 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
980 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
981 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
982 phy-names = "sata-phy";
Michal Simekce906542020-11-26 14:25:02 +0100983 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
Michal Simekcf0bcd72018-03-28 15:43:51 +0200984};
985
986/* SD1 with level shifter */
987&sdhci1 {
988 status = "okay";
Manish Narani12ffe752020-02-13 23:37:30 -0700989 /*
990 * This property should be removed for supporting UHS mode
991 */
992 no-1-8-v;
Michal Simekbd008492021-05-10 13:14:02 +0200993 pinctrl-names = "default";
994 pinctrl-0 = <&pinctrl_sdhci1_default>;
Michal Simek01a6da12020-07-22 17:42:43 +0200995 xlnx,mio-bank = <1>;
Michal Simekcf0bcd72018-03-28 15:43:51 +0200996};
997
Michal Simekcf0bcd72018-03-28 15:43:51 +0200998&uart0 {
999 status = "okay";
Michal Simekbd008492021-05-10 13:14:02 +02001000 pinctrl-names = "default";
1001 pinctrl-0 = <&pinctrl_uart0_default>;
Michal Simekcf0bcd72018-03-28 15:43:51 +02001002};
1003
1004&uart1 {
1005 status = "okay";
Michal Simekbd008492021-05-10 13:14:02 +02001006 pinctrl-names = "default";
1007 pinctrl-0 = <&pinctrl_uart1_default>;
Michal Simekcf0bcd72018-03-28 15:43:51 +02001008};
1009
1010/* ULPI SMSC USB3320 */
1011&usb0 {
1012 status = "okay";
Michal Simekbd008492021-05-10 13:14:02 +02001013 pinctrl-names = "default";
1014 pinctrl-0 = <&pinctrl_usb0_default>;
Manish Narani15ca9eb2021-07-14 06:17:19 -06001015 phy-names = "usb3-phy";
1016 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
Michal Simekcf0bcd72018-03-28 15:43:51 +02001017};
1018
1019&dwc3_0 {
1020 status = "okay";
1021 dr_mode = "host";
1022 snps,usb3_lpm_capable;
Michal Simek184309b2021-05-31 17:51:58 +02001023 maximum-speed = "super-speed";
Michal Simekcf0bcd72018-03-28 15:43:51 +02001024};
1025
1026&watchdog0 {
1027 status = "okay";
1028};
Michal Simekf2b5dd32021-05-27 13:44:35 +02001029
1030&zynqmp_dpdma {
1031 status = "okay";
1032};
1033
1034&zynqmp_dpsub {
1035 status = "okay";
1036 phy-names = "dp-phy0", "dp-phy1";
1037 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
1038 <&psgtr 0 PHY_TYPE_DP 1 3>;
1039};