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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa / . / src / arm / nxp / imx / imx6ul-pico.dtsi
blob: 07dcecbe485dca41b66f3deef932f750d31f5544 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Copyright 2015 Technexion Ltd.
4//
5// Author: Wig Cheng <wig.cheng@technexion.com>
6// Richard Hu <richard.hu@technexion.com>
7// Tapani Utriainen <tapani@technexion.com>
8/dts-v1/;
9
10#include "imx6ul.dtsi"
11
12/ {
13 /* Will be filled by the bootloader */
14 memory@80000000 {
15 device_type = "memory";
16 reg = <0x80000000 0>;
17 };
18
19 chosen {
20 stdout-path = &uart6;
21 };
22
23 backlight: backlight {
24 compatible = "pwm-backlight";
25 pwms = <&pwm3 0 5000000>;
26 brightness-levels = <0 4 8 16 32 64 128 255>;
27 default-brightness-level = <6>;
28 status = "okay";
29 };
30
31 reg_2p5v: regulator-2p5v {
32 compatible = "regulator-fixed";
33 regulator-name = "2P5V";
34 regulator-min-microvolt = <2500000>;
35 regulator-max-microvolt = <2500000>;
36 };
37
38 reg_3p3v: regulator-3p3v {
39 compatible = "regulator-fixed";
40 regulator-name = "3P3V";
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
43 };
44
45 reg_sd1_vmmc: regulator-sd1-vmmc {
46 compatible = "regulator-fixed";
47 regulator-name = "VSD_3V3";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
51 enable-active-high;
52 };
53
54 reg_usb_otg_vbus: regulator-usb-otg-vbus {
55 compatible = "regulator-fixed";
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_usb_otg1>;
58 regulator-name = "usb_otg_vbus";
59 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <5000000>;
61 gpio = <&gpio1 6 0>;
62 };
63
64 reg_brcm: regulator-brcm {
65 compatible = "regulator-fixed";
66 enable-active-high;
67 gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_brcm_reg>;
70 regulator-name = "brcm_reg";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 startup-delay-us = <200000>;
74 };
75
76 panel {
77 compatible = "vxt,vl050-8048nt-c01";
78 backlight = <&backlight>;
79
80 port {
81 panel_in: endpoint {
82 remote-endpoint = <&display_out>;
83 };
84 };
85 };
86};
87
88&can1 {
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_flexcan1>;
91 status = "okay";
92};
93
94&can2 {
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_flexcan2>;
97 status = "okay";
98};
99
100&clks {
101 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
102 assigned-clock-rates = <786432000>;
103};
104
105&fec2 {
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_enet2>;
108 phy-mode = "rmii";
109 phy-handle = <&ethphy1>;
110 status = "okay";
111 phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
112 phy-reset-duration = <1>;
113
114 mdio {
115 #address-cells = <1>;
116 #size-cells = <0>;
117
118 ethphy1: ethernet-phy@1 {
119 compatible = "ethernet-phy-ieee802.3-c22";
120 reg = <1>;
121 max-speed = <100>;
122 interrupt-parent = <&gpio5>;
123 interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
124 clocks = <&clks IMX6UL_CLK_ENET_REF>;
125 clock-names = "rmii-ref";
126 };
127 };
128};
129
130&i2c1 {
131 clock-frequency = <100000>;
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_i2c1>;
134 status = "okay";
135
136 pmic: pmic@8 {
137 compatible = "fsl,pfuze3000";
138 reg = <0x08>;
139
140 regulators {
141 /* VDD_ARM_SOC_IN*/
142 sw1b_reg: sw1b {
143 regulator-min-microvolt = <700000>;
144 regulator-max-microvolt = <1475000>;
145 regulator-boot-on;
146 regulator-always-on;
147 regulator-ramp-delay = <6250>;
148 };
149
150 /* DRAM */
151 sw3a_reg: sw3 {
152 regulator-min-microvolt = <900000>;
153 regulator-max-microvolt = <1650000>;
154 regulator-boot-on;
155 regulator-always-on;
156 };
157
158 /* DRAM */
159 vref_reg: vrefddr {
160 regulator-boot-on;
161 regulator-always-on;
162 };
163 };
164 };
165};
166
167&lcdif {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
170 status = "okay";
171
172 port {
173 display_out: endpoint {
174 remote-endpoint = <&panel_in>;
175 };
176 };
177};
178
179&pwm3 {
180 #pwm-cells = <2>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_pwm3>;
183 status = "okay";
184};
185
186&pwm7 {
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_pwm7>;
189 status = "okay";
190};
191
192&pwm8 {
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_pwm8>;
195 status = "okay";
196};
197
198&sai1 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_sai1>;
201 status = "okay";
202};
203
204&uart3 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_uart3>;
207 uart-has-rtscts;
208 status = "okay";
209};
210
211&uart6 {
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_uart6>;
214 status = "okay";
215};
216
217&usbotg1 {
218 vbus-supply = <&reg_usb_otg_vbus>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_usb_otg1_id>;
221 dr_mode = "otg";
222 disable-over-current;
223 status = "okay";
224};
225
226&usbotg2 {
227 dr_mode = "host";
228 disable-over-current;
229 status = "okay";
230};
231
232&usdhc1 {
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_usdhc1>;
235 bus-width = <8>;
236 no-1-8-v;
237 non-removable;
238 keep-power-in-suspend;
239 status = "okay";
240};
241
242&usdhc2 { /* Wifi SDIO */
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_usdhc2>;
245 no-1-8-v;
246 non-removable;
247 keep-power-in-suspend;
248 wakeup-source;
249 vmmc-supply = <&reg_brcm>;
250 status = "okay";
251};
252
253&wdog1 {
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_wdog>;
256 fsl,ext-reset-output;
257};
258
259&iomuxc {
260 pinctrl_brcm_reg: brcmreggrp {
261 fsl,pins = <
262 MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */
263 MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */
264 >;
265 };
266
267 pinctrl_enet2: enet2grp {
268 fsl,pins = <
269 MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0
270 MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0
271 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
272 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
273 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
274 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
275 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
276 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
277 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
278 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
279 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800
280 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79
281 >;
282 };
283
284 pinctrl_flexcan1: flexcan1grp {
285 fsl,pins = <
286 MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
287 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
288 >;
289 };
290
291 pinctrl_flexcan2: flexcan2grp {
292 fsl,pins = <
293 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
294 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
295 >;
296 };
297
298 pinctrl_i2c1: i2c1grp {
299 fsl,pins = <
300 MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0
301 MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0
302 >;
303 };
304
305 pinctrl_i2c2: i2c2grp {
306 fsl,pins = <
307 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
308 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
309 >;
310 };
311
312 pinctrl_i2c3: i2c3grp {
313 fsl,pins = <
314 MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0
315 MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0
316 >;
317 };
318
319 pinctrl_lcdif_dat: lcdifdatgrp {
320 fsl,pins = <
321 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
322 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
323 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
324 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
325 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
326 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
327 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
328 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
329 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
330 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
331 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
332 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
333 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
334 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
335 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
336 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
337 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
338 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
339 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
340 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
341 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
342 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
343 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
344 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
345 >;
346 };
347
348 pinctrl_lcdif_ctrl: lcdifctrlgrp {
349 fsl,pins = <
350 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
351 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
352 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
353 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
354 /* LCD reset */
355 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
356 >;
357 };
358
359 pinctrl_pwm3: pwm3grp {
360 fsl,pins = <
361 MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0
362 >;
363 };
364
365 pinctrl_pwm7: pwm7grp {
366 fsl,pins = <
367 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0
368 >;
369 };
370
371 pinctrl_pwm8: pwm8grp {
372 fsl,pins = <
373 MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
374 >;
375 };
376
377 pinctrl_sai1: sai1grp {
378 fsl,pins = <
379 MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0
380 MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0
381 MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
382 MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
383 >;
384 };
385
386 pinctrl_uart3: uart3grp {
387 fsl,pins = <
388 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0
389 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0
390 MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0
391 MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0
392 >;
393 };
394
395 pinctrl_uart5: uart5grp {
396 fsl,pins = <
397 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1
398 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1
399 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
400 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
401 >;
402 };
403
404 pinctrl_uart6: uart6grp {
405 fsl,pins = <
406 MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
407 MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
408 >;
409 };
410
411 pinctrl_usb_otg1: usbotg1grp {
412 fsl,pins = <
413 MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0
414 >;
415 };
416
417 pinctrl_usb_otg1_id: usbotg1idgrp {
418 fsl,pins = <
419 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
420 >;
421 };
422
423 pinctrl_usdhc1: usdhc1grp {
424 fsl,pins = <
425 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
426 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
427 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
428 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
429 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
430 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
431 MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029
432 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
433 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
434 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
435 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
436 >;
437 };
438
439 pinctrl_usdhc2: usdhc2grp {
440 fsl,pins = <
441 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
442 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
443 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
444 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
445 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
446 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
447 >;
448 };
449
450 pinctrl_wdog: wdoggrp {
451 fsl,pins = <
452 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
453 >;
454 };
455};