Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa / . / src / riscv / starfive / jh7110.dtsi
blob: 4a5708f7fcf7292f63fe975f3fd26cd7becc90d2 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/starfive,jh7110-crg.h>
9#include <dt-bindings/power/starfive,jh7110-pmu.h>
10#include <dt-bindings/reset/starfive,jh7110-crg.h>
11#include <dt-bindings/thermal/thermal.h>
12
13/ {
14 compatible = "starfive,jh7110";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 S7_0: cpu@0 {
23 compatible = "sifive,s7", "riscv";
24 reg = <0>;
25 device_type = "cpu";
26 i-cache-block-size = <64>;
27 i-cache-sets = <64>;
28 i-cache-size = <16384>;
29 next-level-cache = <&ccache>;
30 riscv,isa = "rv64imac_zba_zbb";
31 riscv,isa-base = "rv64i";
32 riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",
33 "zifencei", "zihpm";
34 status = "disabled";
35
36 cpu0_intc: interrupt-controller {
37 compatible = "riscv,cpu-intc";
38 interrupt-controller;
39 #interrupt-cells = <1>;
40 };
41 };
42
43 U74_1: cpu@1 {
44 compatible = "sifive,u74-mc", "riscv";
45 reg = <1>;
46 d-cache-block-size = <64>;
47 d-cache-sets = <64>;
48 d-cache-size = <32768>;
49 d-tlb-sets = <1>;
50 d-tlb-size = <40>;
51 device_type = "cpu";
52 i-cache-block-size = <64>;
53 i-cache-sets = <64>;
54 i-cache-size = <32768>;
55 i-tlb-sets = <1>;
56 i-tlb-size = <40>;
57 mmu-type = "riscv,sv39";
58 next-level-cache = <&ccache>;
59 riscv,isa = "rv64imafdc_zba_zbb";
60 riscv,isa-base = "rv64i";
61 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
62 "zicsr", "zifencei", "zihpm";
63 tlb-split;
64 operating-points-v2 = <&cpu_opp>;
65 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
66 clock-names = "cpu";
67 #cooling-cells = <2>;
68
69 cpu1_intc: interrupt-controller {
70 compatible = "riscv,cpu-intc";
71 interrupt-controller;
72 #interrupt-cells = <1>;
73 };
74 };
75
76 U74_2: cpu@2 {
77 compatible = "sifive,u74-mc", "riscv";
78 reg = <2>;
79 d-cache-block-size = <64>;
80 d-cache-sets = <64>;
81 d-cache-size = <32768>;
82 d-tlb-sets = <1>;
83 d-tlb-size = <40>;
84 device_type = "cpu";
85 i-cache-block-size = <64>;
86 i-cache-sets = <64>;
87 i-cache-size = <32768>;
88 i-tlb-sets = <1>;
89 i-tlb-size = <40>;
90 mmu-type = "riscv,sv39";
91 next-level-cache = <&ccache>;
92 riscv,isa = "rv64imafdc_zba_zbb";
93 riscv,isa-base = "rv64i";
94 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
95 "zicsr", "zifencei", "zihpm";
96 tlb-split;
97 operating-points-v2 = <&cpu_opp>;
98 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
99 clock-names = "cpu";
100 #cooling-cells = <2>;
101
102 cpu2_intc: interrupt-controller {
103 compatible = "riscv,cpu-intc";
104 interrupt-controller;
105 #interrupt-cells = <1>;
106 };
107 };
108
109 U74_3: cpu@3 {
110 compatible = "sifive,u74-mc", "riscv";
111 reg = <3>;
112 d-cache-block-size = <64>;
113 d-cache-sets = <64>;
114 d-cache-size = <32768>;
115 d-tlb-sets = <1>;
116 d-tlb-size = <40>;
117 device_type = "cpu";
118 i-cache-block-size = <64>;
119 i-cache-sets = <64>;
120 i-cache-size = <32768>;
121 i-tlb-sets = <1>;
122 i-tlb-size = <40>;
123 mmu-type = "riscv,sv39";
124 next-level-cache = <&ccache>;
125 riscv,isa = "rv64imafdc_zba_zbb";
126 riscv,isa-base = "rv64i";
127 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
128 "zicsr", "zifencei", "zihpm";
129 tlb-split;
130 operating-points-v2 = <&cpu_opp>;
131 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
132 clock-names = "cpu";
133 #cooling-cells = <2>;
134
135 cpu3_intc: interrupt-controller {
136 compatible = "riscv,cpu-intc";
137 interrupt-controller;
138 #interrupt-cells = <1>;
139 };
140 };
141
142 U74_4: cpu@4 {
143 compatible = "sifive,u74-mc", "riscv";
144 reg = <4>;
145 d-cache-block-size = <64>;
146 d-cache-sets = <64>;
147 d-cache-size = <32768>;
148 d-tlb-sets = <1>;
149 d-tlb-size = <40>;
150 device_type = "cpu";
151 i-cache-block-size = <64>;
152 i-cache-sets = <64>;
153 i-cache-size = <32768>;
154 i-tlb-sets = <1>;
155 i-tlb-size = <40>;
156 mmu-type = "riscv,sv39";
157 next-level-cache = <&ccache>;
158 riscv,isa = "rv64imafdc_zba_zbb";
159 riscv,isa-base = "rv64i";
160 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
161 "zicsr", "zifencei", "zihpm";
162 tlb-split;
163 operating-points-v2 = <&cpu_opp>;
164 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
165 clock-names = "cpu";
166 #cooling-cells = <2>;
167
168 cpu4_intc: interrupt-controller {
169 compatible = "riscv,cpu-intc";
170 interrupt-controller;
171 #interrupt-cells = <1>;
172 };
173 };
174
175 cpu-map {
176 cluster0 {
177 core0 {
178 cpu = <&S7_0>;
179 };
180
181 core1 {
182 cpu = <&U74_1>;
183 };
184
185 core2 {
186 cpu = <&U74_2>;
187 };
188
189 core3 {
190 cpu = <&U74_3>;
191 };
192
193 core4 {
194 cpu = <&U74_4>;
195 };
196 };
197 };
198 };
199
200 cpu_opp: opp-table-0 {
201 compatible = "operating-points-v2";
202 opp-shared;
203 opp-375000000 {
204 opp-hz = /bits/ 64 <375000000>;
205 opp-microvolt = <800000>;
206 };
207 opp-500000000 {
208 opp-hz = /bits/ 64 <500000000>;
209 opp-microvolt = <800000>;
210 };
211 opp-750000000 {
212 opp-hz = /bits/ 64 <750000000>;
213 opp-microvolt = <800000>;
214 };
215 opp-1500000000 {
216 opp-hz = /bits/ 64 <1500000000>;
217 opp-microvolt = <1040000>;
218 };
219 };
220
221 thermal-zones {
222 cpu-thermal {
223 polling-delay-passive = <250>;
224 polling-delay = <15000>;
225
226 thermal-sensors = <&sfctemp>;
227
228 cooling-maps {
229 map0 {
230 trip = <&cpu_alert0>;
231 cooling-device =
232 <&U74_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
233 <&U74_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
234 <&U74_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
235 <&U74_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
236 };
237 };
238
239 trips {
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]240 cpu_alert0: cpu-alert0 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]241 /* milliCelsius */
242 temperature = <85000>;
243 hysteresis = <2000>;
244 type = "passive";
245 };
246
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]247 cpu-crit {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]248 /* milliCelsius */
249 temperature = <100000>;
250 hysteresis = <2000>;
251 type = "critical";
252 };
253 };
254 };
255 };
256
257 dvp_clk: dvp-clock {
258 compatible = "fixed-clock";
259 clock-output-names = "dvp_clk";
260 #clock-cells = <0>;
261 };
262 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
263 compatible = "fixed-clock";
264 clock-output-names = "gmac0_rgmii_rxin";
265 #clock-cells = <0>;
266 };
267
268 gmac0_rmii_refin: gmac0-rmii-refin-clock {
269 compatible = "fixed-clock";
270 clock-output-names = "gmac0_rmii_refin";
271 #clock-cells = <0>;
272 };
273
274 gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
275 compatible = "fixed-clock";
276 clock-output-names = "gmac1_rgmii_rxin";
277 #clock-cells = <0>;
278 };
279
280 gmac1_rmii_refin: gmac1-rmii-refin-clock {
281 compatible = "fixed-clock";
282 clock-output-names = "gmac1_rmii_refin";
283 #clock-cells = <0>;
284 };
285
286 hdmitx0_pixelclk: hdmitx0-pixel-clock {
287 compatible = "fixed-clock";
288 clock-output-names = "hdmitx0_pixelclk";
289 #clock-cells = <0>;
290 };
291
292 i2srx_bclk_ext: i2srx-bclk-ext-clock {
293 compatible = "fixed-clock";
294 clock-output-names = "i2srx_bclk_ext";
295 #clock-cells = <0>;
296 };
297
298 i2srx_lrck_ext: i2srx-lrck-ext-clock {
299 compatible = "fixed-clock";
300 clock-output-names = "i2srx_lrck_ext";
301 #clock-cells = <0>;
302 };
303
304 i2stx_bclk_ext: i2stx-bclk-ext-clock {
305 compatible = "fixed-clock";
306 clock-output-names = "i2stx_bclk_ext";
307 #clock-cells = <0>;
308 };
309
310 i2stx_lrck_ext: i2stx-lrck-ext-clock {
311 compatible = "fixed-clock";
312 clock-output-names = "i2stx_lrck_ext";
313 #clock-cells = <0>;
314 };
315
316 mclk_ext: mclk-ext-clock {
317 compatible = "fixed-clock";
318 clock-output-names = "mclk_ext";
319 #clock-cells = <0>;
320 };
321
322 osc: oscillator {
323 compatible = "fixed-clock";
324 clock-output-names = "osc";
325 #clock-cells = <0>;
326 };
327
328 rtc_osc: rtc-oscillator {
329 compatible = "fixed-clock";
330 clock-output-names = "rtc_osc";
331 #clock-cells = <0>;
332 };
333
334 stmmac_axi_setup: stmmac-axi-config {
335 snps,lpi_en;
336 snps,wr_osr_lmt = <15>;
337 snps,rd_osr_lmt = <15>;
338 snps,blen = <256 128 64 32 0 0 0>;
339 };
340
341 tdm_ext: tdm-ext-clock {
342 compatible = "fixed-clock";
343 clock-output-names = "tdm_ext";
344 #clock-cells = <0>;
345 };
346
347 soc {
348 compatible = "simple-bus";
349 interrupt-parent = <&plic>;
350 #address-cells = <2>;
351 #size-cells = <2>;
352 ranges;
353
354 clint: timer@2000000 {
355 compatible = "starfive,jh7110-clint", "sifive,clint0";
356 reg = <0x0 0x2000000 0x0 0x10000>;
357 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
358 <&cpu1_intc 3>, <&cpu1_intc 7>,
359 <&cpu2_intc 3>, <&cpu2_intc 7>,
360 <&cpu3_intc 3>, <&cpu3_intc 7>,
361 <&cpu4_intc 3>, <&cpu4_intc 7>;
362 };
363
364 ccache: cache-controller@2010000 {
365 compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
366 reg = <0x0 0x2010000 0x0 0x4000>;
367 interrupts = <1>, <3>, <4>, <2>;
368 cache-block-size = <64>;
369 cache-level = <2>;
370 cache-sets = <2048>;
371 cache-size = <2097152>;
372 cache-unified;
373 };
374
375 plic: interrupt-controller@c000000 {
376 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
377 reg = <0x0 0xc000000 0x0 0x4000000>;
378 interrupts-extended = <&cpu0_intc 11>,
379 <&cpu1_intc 11>, <&cpu1_intc 9>,
380 <&cpu2_intc 11>, <&cpu2_intc 9>,
381 <&cpu3_intc 11>, <&cpu3_intc 9>,
382 <&cpu4_intc 11>, <&cpu4_intc 9>;
383 interrupt-controller;
384 #interrupt-cells = <1>;
385 #address-cells = <0>;
386 riscv,ndev = <136>;
387 };
388
389 uart0: serial@10000000 {
390 compatible = "snps,dw-apb-uart";
391 reg = <0x0 0x10000000 0x0 0x10000>;
392 clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
393 <&syscrg JH7110_SYSCLK_UART0_APB>;
394 clock-names = "baudclk", "apb_pclk";
395 resets = <&syscrg JH7110_SYSRST_UART0_APB>;
396 interrupts = <32>;
397 reg-io-width = <4>;
398 reg-shift = <2>;
399 status = "disabled";
400 };
401
402 uart1: serial@10010000 {
403 compatible = "snps,dw-apb-uart";
404 reg = <0x0 0x10010000 0x0 0x10000>;
405 clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
406 <&syscrg JH7110_SYSCLK_UART1_APB>;
407 clock-names = "baudclk", "apb_pclk";
408 resets = <&syscrg JH7110_SYSRST_UART1_APB>;
409 interrupts = <33>;
410 reg-io-width = <4>;
411 reg-shift = <2>;
412 status = "disabled";
413 };
414
415 uart2: serial@10020000 {
416 compatible = "snps,dw-apb-uart";
417 reg = <0x0 0x10020000 0x0 0x10000>;
418 clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
419 <&syscrg JH7110_SYSCLK_UART2_APB>;
420 clock-names = "baudclk", "apb_pclk";
421 resets = <&syscrg JH7110_SYSRST_UART2_APB>;
422 interrupts = <34>;
423 reg-io-width = <4>;
424 reg-shift = <2>;
425 status = "disabled";
426 };
427
428 i2c0: i2c@10030000 {
429 compatible = "snps,designware-i2c";
430 reg = <0x0 0x10030000 0x0 0x10000>;
431 clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
432 clock-names = "ref";
433 resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
434 interrupts = <35>;
435 #address-cells = <1>;
436 #size-cells = <0>;
437 status = "disabled";
438 };
439
440 i2c1: i2c@10040000 {
441 compatible = "snps,designware-i2c";
442 reg = <0x0 0x10040000 0x0 0x10000>;
443 clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
444 clock-names = "ref";
445 resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
446 interrupts = <36>;
447 #address-cells = <1>;
448 #size-cells = <0>;
449 status = "disabled";
450 };
451
452 i2c2: i2c@10050000 {
453 compatible = "snps,designware-i2c";
454 reg = <0x0 0x10050000 0x0 0x10000>;
455 clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
456 clock-names = "ref";
457 resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
458 interrupts = <37>;
459 #address-cells = <1>;
460 #size-cells = <0>;
461 status = "disabled";
462 };
463
464 spi0: spi@10060000 {
465 compatible = "arm,pl022", "arm,primecell";
466 reg = <0x0 0x10060000 0x0 0x10000>;
467 clocks = <&syscrg JH7110_SYSCLK_SPI0_APB>,
468 <&syscrg JH7110_SYSCLK_SPI0_APB>;
469 clock-names = "sspclk", "apb_pclk";
470 resets = <&syscrg JH7110_SYSRST_SPI0_APB>;
471 interrupts = <38>;
472 arm,primecell-periphid = <0x00041022>;
473 num-cs = <1>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 status = "disabled";
477 };
478
479 spi1: spi@10070000 {
480 compatible = "arm,pl022", "arm,primecell";
481 reg = <0x0 0x10070000 0x0 0x10000>;
482 clocks = <&syscrg JH7110_SYSCLK_SPI1_APB>,
483 <&syscrg JH7110_SYSCLK_SPI1_APB>;
484 clock-names = "sspclk", "apb_pclk";
485 resets = <&syscrg JH7110_SYSRST_SPI1_APB>;
486 interrupts = <39>;
487 arm,primecell-periphid = <0x00041022>;
488 num-cs = <1>;
489 #address-cells = <1>;
490 #size-cells = <0>;
491 status = "disabled";
492 };
493
494 spi2: spi@10080000 {
495 compatible = "arm,pl022", "arm,primecell";
496 reg = <0x0 0x10080000 0x0 0x10000>;
497 clocks = <&syscrg JH7110_SYSCLK_SPI2_APB>,
498 <&syscrg JH7110_SYSCLK_SPI2_APB>;
499 clock-names = "sspclk", "apb_pclk";
500 resets = <&syscrg JH7110_SYSRST_SPI2_APB>;
501 interrupts = <40>;
502 arm,primecell-periphid = <0x00041022>;
503 num-cs = <1>;
504 #address-cells = <1>;
505 #size-cells = <0>;
506 status = "disabled";
507 };
508
509 tdm: tdm@10090000 {
510 compatible = "starfive,jh7110-tdm";
511 reg = <0x0 0x10090000 0x0 0x1000>;
512 clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>,
513 <&syscrg JH7110_SYSCLK_TDM_APB>,
514 <&syscrg JH7110_SYSCLK_TDM_INTERNAL>,
515 <&syscrg JH7110_SYSCLK_TDM_TDM>,
516 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
517 <&tdm_ext>;
518 clock-names = "tdm_ahb", "tdm_apb",
519 "tdm_internal", "tdm",
520 "mclk_inner", "tdm_ext";
521 resets = <&syscrg JH7110_SYSRST_TDM_AHB>,
522 <&syscrg JH7110_SYSRST_TDM_APB>,
523 <&syscrg JH7110_SYSRST_TDM_CORE>;
524 dmas = <&dma 20>, <&dma 21>;
525 dma-names = "rx","tx";
526 #sound-dai-cells = <0>;
527 status = "disabled";
528 };
529
530 i2srx: i2s@100e0000 {
531 compatible = "starfive,jh7110-i2srx";
532 reg = <0x0 0x100e0000 0x0 0x1000>;
533 clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>,
534 <&syscrg JH7110_SYSCLK_I2SRX_APB>,
535 <&syscrg JH7110_SYSCLK_MCLK>,
536 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
537 <&mclk_ext>,
538 <&syscrg JH7110_SYSCLK_I2SRX_BCLK>,
539 <&syscrg JH7110_SYSCLK_I2SRX_LRCK>,
540 <&i2srx_bclk_ext>,
541 <&i2srx_lrck_ext>;
542 clock-names = "i2sclk", "apb", "mclk",
543 "mclk_inner", "mclk_ext", "bclk",
544 "lrck", "bclk_ext", "lrck_ext";
545 resets = <&syscrg JH7110_SYSRST_I2SRX_APB>,
546 <&syscrg JH7110_SYSRST_I2SRX_BCLK>;
547 dmas = <0>, <&dma 24>;
548 dma-names = "tx", "rx";
549 starfive,syscon = <&sys_syscon 0x18 0x2>;
550 #sound-dai-cells = <0>;
551 status = "disabled";
552 };
553
554 pwmdac: pwmdac@100b0000 {
555 compatible = "starfive,jh7110-pwmdac";
556 reg = <0x0 0x100b0000 0x0 0x1000>;
557 clocks = <&syscrg JH7110_SYSCLK_PWMDAC_APB>,
558 <&syscrg JH7110_SYSCLK_PWMDAC_CORE>;
559 clock-names = "apb", "core";
560 resets = <&syscrg JH7110_SYSRST_PWMDAC_APB>;
561 dmas = <&dma 22>;
562 dma-names = "tx";
563 #sound-dai-cells = <0>;
564 status = "disabled";
565 };
566
567 usb0: usb@10100000 {
568 compatible = "starfive,jh7110-usb";
569 ranges = <0x0 0x0 0x10100000 0x100000>;
570 #address-cells = <1>;
571 #size-cells = <1>;
572 starfive,stg-syscon = <&stg_syscon 0x4>;
573 clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
574 <&stgcrg JH7110_STGCLK_USB0_STB>,
575 <&stgcrg JH7110_STGCLK_USB0_APB>,
576 <&stgcrg JH7110_STGCLK_USB0_AXI>,
577 <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
578 clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
579 resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
580 <&stgcrg JH7110_STGRST_USB0_APB>,
581 <&stgcrg JH7110_STGRST_USB0_AXI>,
582 <&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
583 reset-names = "pwrup", "apb", "axi", "utmi_apb";
584 status = "disabled";
585
586 usb_cdns3: usb@0 {
587 compatible = "cdns,usb3";
588 reg = <0x0 0x10000>,
589 <0x10000 0x10000>,
590 <0x20000 0x10000>;
591 reg-names = "otg", "xhci", "dev";
592 interrupts = <100>, <108>, <110>;
593 interrupt-names = "host", "peripheral", "otg";
594 phys = <&usbphy0>;
595 phy-names = "cdns3,usb2-phy";
596 };
597 };
598
599 usbphy0: phy@10200000 {
600 compatible = "starfive,jh7110-usb-phy";
601 reg = <0x0 0x10200000 0x0 0x10000>;
602 clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
603 <&stgcrg JH7110_STGCLK_USB0_APP_125>;
604 clock-names = "125m", "app_125m";
605 #phy-cells = <0>;
606 };
607
608 pciephy0: phy@10210000 {
609 compatible = "starfive,jh7110-pcie-phy";
610 reg = <0x0 0x10210000 0x0 0x10000>;
611 #phy-cells = <0>;
612 };
613
614 pciephy1: phy@10220000 {
615 compatible = "starfive,jh7110-pcie-phy";
616 reg = <0x0 0x10220000 0x0 0x10000>;
617 #phy-cells = <0>;
618 };
619
620 stgcrg: clock-controller@10230000 {
621 compatible = "starfive,jh7110-stgcrg";
622 reg = <0x0 0x10230000 0x0 0x10000>;
623 clocks = <&osc>,
624 <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
625 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
626 <&syscrg JH7110_SYSCLK_USB_125M>,
627 <&syscrg JH7110_SYSCLK_CPU_BUS>,
628 <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
629 <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
630 <&syscrg JH7110_SYSCLK_APB_BUS>;
631 clock-names = "osc", "hifi4_core",
632 "stg_axiahb", "usb_125m",
633 "cpu_bus", "hifi4_axi",
634 "nocstg_bus", "apb_bus";
635 #clock-cells = <1>;
636 #reset-cells = <1>;
637 };
638
639 stg_syscon: syscon@10240000 {
640 compatible = "starfive,jh7110-stg-syscon", "syscon";
641 reg = <0x0 0x10240000 0x0 0x1000>;
642 };
643
644 uart3: serial@12000000 {
645 compatible = "snps,dw-apb-uart";
646 reg = <0x0 0x12000000 0x0 0x10000>;
647 clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
648 <&syscrg JH7110_SYSCLK_UART3_APB>;
649 clock-names = "baudclk", "apb_pclk";
650 resets = <&syscrg JH7110_SYSRST_UART3_APB>;
651 interrupts = <45>;
652 reg-io-width = <4>;
653 reg-shift = <2>;
654 status = "disabled";
655 };
656
657 uart4: serial@12010000 {
658 compatible = "snps,dw-apb-uart";
659 reg = <0x0 0x12010000 0x0 0x10000>;
660 clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
661 <&syscrg JH7110_SYSCLK_UART4_APB>;
662 clock-names = "baudclk", "apb_pclk";
663 resets = <&syscrg JH7110_SYSRST_UART4_APB>;
664 interrupts = <46>;
665 reg-io-width = <4>;
666 reg-shift = <2>;
667 status = "disabled";
668 };
669
670 uart5: serial@12020000 {
671 compatible = "snps,dw-apb-uart";
672 reg = <0x0 0x12020000 0x0 0x10000>;
673 clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
674 <&syscrg JH7110_SYSCLK_UART5_APB>;
675 clock-names = "baudclk", "apb_pclk";
676 resets = <&syscrg JH7110_SYSRST_UART5_APB>;
677 interrupts = <47>;
678 reg-io-width = <4>;
679 reg-shift = <2>;
680 status = "disabled";
681 };
682
683 i2c3: i2c@12030000 {
684 compatible = "snps,designware-i2c";
685 reg = <0x0 0x12030000 0x0 0x10000>;
686 clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
687 clock-names = "ref";
688 resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
689 interrupts = <48>;
690 #address-cells = <1>;
691 #size-cells = <0>;
692 status = "disabled";
693 };
694
695 i2c4: i2c@12040000 {
696 compatible = "snps,designware-i2c";
697 reg = <0x0 0x12040000 0x0 0x10000>;
698 clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
699 clock-names = "ref";
700 resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
701 interrupts = <49>;
702 #address-cells = <1>;
703 #size-cells = <0>;
704 status = "disabled";
705 };
706
707 i2c5: i2c@12050000 {
708 compatible = "snps,designware-i2c";
709 reg = <0x0 0x12050000 0x0 0x10000>;
710 clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
711 clock-names = "ref";
712 resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
713 interrupts = <50>;
714 #address-cells = <1>;
715 #size-cells = <0>;
716 status = "disabled";
717 };
718
719 i2c6: i2c@12060000 {
720 compatible = "snps,designware-i2c";
721 reg = <0x0 0x12060000 0x0 0x10000>;
722 clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
723 clock-names = "ref";
724 resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
725 interrupts = <51>;
726 #address-cells = <1>;
727 #size-cells = <0>;
728 status = "disabled";
729 };
730
731 spi3: spi@12070000 {
732 compatible = "arm,pl022", "arm,primecell";
733 reg = <0x0 0x12070000 0x0 0x10000>;
734 clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>,
735 <&syscrg JH7110_SYSCLK_SPI3_APB>;
736 clock-names = "sspclk", "apb_pclk";
737 resets = <&syscrg JH7110_SYSRST_SPI3_APB>;
738 interrupts = <52>;
739 arm,primecell-periphid = <0x00041022>;
740 num-cs = <1>;
741 #address-cells = <1>;
742 #size-cells = <0>;
743 status = "disabled";
744 };
745
746 spi4: spi@12080000 {
747 compatible = "arm,pl022", "arm,primecell";
748 reg = <0x0 0x12080000 0x0 0x10000>;
749 clocks = <&syscrg JH7110_SYSCLK_SPI4_APB>,
750 <&syscrg JH7110_SYSCLK_SPI4_APB>;
751 clock-names = "sspclk", "apb_pclk";
752 resets = <&syscrg JH7110_SYSRST_SPI4_APB>;
753 interrupts = <53>;
754 arm,primecell-periphid = <0x00041022>;
755 num-cs = <1>;
756 #address-cells = <1>;
757 #size-cells = <0>;
758 status = "disabled";
759 };
760
761 spi5: spi@12090000 {
762 compatible = "arm,pl022", "arm,primecell";
763 reg = <0x0 0x12090000 0x0 0x10000>;
764 clocks = <&syscrg JH7110_SYSCLK_SPI5_APB>,
765 <&syscrg JH7110_SYSCLK_SPI5_APB>;
766 clock-names = "sspclk", "apb_pclk";
767 resets = <&syscrg JH7110_SYSRST_SPI5_APB>;
768 interrupts = <54>;
769 arm,primecell-periphid = <0x00041022>;
770 num-cs = <1>;
771 #address-cells = <1>;
772 #size-cells = <0>;
773 status = "disabled";
774 };
775
776 spi6: spi@120a0000 {
777 compatible = "arm,pl022", "arm,primecell";
778 reg = <0x0 0x120A0000 0x0 0x10000>;
779 clocks = <&syscrg JH7110_SYSCLK_SPI6_APB>,
780 <&syscrg JH7110_SYSCLK_SPI6_APB>;
781 clock-names = "sspclk", "apb_pclk";
782 resets = <&syscrg JH7110_SYSRST_SPI6_APB>;
783 interrupts = <55>;
784 arm,primecell-periphid = <0x00041022>;
785 num-cs = <1>;
786 #address-cells = <1>;
787 #size-cells = <0>;
788 status = "disabled";
789 };
790
791 i2stx0: i2s@120b0000 {
792 compatible = "starfive,jh7110-i2stx0";
793 reg = <0x0 0x120b0000 0x0 0x1000>;
794 clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>,
795 <&syscrg JH7110_SYSCLK_I2STX0_APB>,
796 <&syscrg JH7110_SYSCLK_MCLK>,
797 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
798 <&mclk_ext>;
799 clock-names = "i2sclk", "apb", "mclk",
800 "mclk_inner","mclk_ext";
801 resets = <&syscrg JH7110_SYSRST_I2STX0_APB>,
802 <&syscrg JH7110_SYSRST_I2STX0_BCLK>;
803 dmas = <&dma 47>;
804 dma-names = "tx";
805 #sound-dai-cells = <0>;
806 status = "disabled";
807 };
808
809 i2stx1: i2s@120c0000 {
810 compatible = "starfive,jh7110-i2stx1";
811 reg = <0x0 0x120c0000 0x0 0x1000>;
812 clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>,
813 <&syscrg JH7110_SYSCLK_I2STX1_APB>,
814 <&syscrg JH7110_SYSCLK_MCLK>,
815 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
816 <&mclk_ext>,
817 <&syscrg JH7110_SYSCLK_I2STX1_BCLK>,
818 <&syscrg JH7110_SYSCLK_I2STX1_LRCK>,
819 <&i2stx_bclk_ext>,
820 <&i2stx_lrck_ext>;
821 clock-names = "i2sclk", "apb", "mclk",
822 "mclk_inner", "mclk_ext", "bclk",
823 "lrck", "bclk_ext", "lrck_ext";
824 resets = <&syscrg JH7110_SYSRST_I2STX1_APB>,
825 <&syscrg JH7110_SYSRST_I2STX1_BCLK>;
826 dmas = <&dma 48>;
827 dma-names = "tx";
828 #sound-dai-cells = <0>;
829 status = "disabled";
830 };
831
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]832 pwm: pwm@120d0000 {
833 compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
834 reg = <0x0 0x120d0000 0x0 0x10000>;
835 clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
836 resets = <&syscrg JH7110_SYSRST_PWM_APB>;
837 #pwm-cells = <3>;
838 status = "disabled";
839 };
840
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]841 sfctemp: temperature-sensor@120e0000 {
842 compatible = "starfive,jh7110-temp";
843 reg = <0x0 0x120e0000 0x0 0x10000>;
844 clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>,
845 <&syscrg JH7110_SYSCLK_TEMP_APB>;
846 clock-names = "sense", "bus";
847 resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
848 <&syscrg JH7110_SYSRST_TEMP_APB>;
849 reset-names = "sense", "bus";
850 #thermal-sensor-cells = <0>;
851 };
852
853 qspi: spi@13010000 {
854 compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
855 reg = <0x0 0x13010000 0x0 0x10000>,
856 <0x0 0x21000000 0x0 0x400000>;
857 interrupts = <25>;
858 clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
859 <&syscrg JH7110_SYSCLK_QSPI_AHB>,
860 <&syscrg JH7110_SYSCLK_QSPI_APB>;
861 clock-names = "ref", "ahb", "apb";
862 resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
863 <&syscrg JH7110_SYSRST_QSPI_AHB>,
864 <&syscrg JH7110_SYSRST_QSPI_REF>;
865 reset-names = "qspi", "qspi-ocp", "rstc_ref";
866 cdns,fifo-depth = <256>;
867 cdns,fifo-width = <4>;
868 cdns,trigger-address = <0x0>;
869 status = "disabled";
870 };
871
872 syscrg: clock-controller@13020000 {
873 compatible = "starfive,jh7110-syscrg";
874 reg = <0x0 0x13020000 0x0 0x10000>;
875 clocks = <&osc>, <&gmac1_rmii_refin>,
876 <&gmac1_rgmii_rxin>,
877 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
878 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
879 <&tdm_ext>, <&mclk_ext>,
880 <&pllclk JH7110_PLLCLK_PLL0_OUT>,
881 <&pllclk JH7110_PLLCLK_PLL1_OUT>,
882 <&pllclk JH7110_PLLCLK_PLL2_OUT>;
883 clock-names = "osc", "gmac1_rmii_refin",
884 "gmac1_rgmii_rxin",
885 "i2stx_bclk_ext", "i2stx_lrck_ext",
886 "i2srx_bclk_ext", "i2srx_lrck_ext",
887 "tdm_ext", "mclk_ext",
888 "pll0_out", "pll1_out", "pll2_out";
889 #clock-cells = <1>;
890 #reset-cells = <1>;
891 };
892
893 sys_syscon: syscon@13030000 {
894 compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
895 reg = <0x0 0x13030000 0x0 0x1000>;
896
897 pllclk: clock-controller {
898 compatible = "starfive,jh7110-pll";
899 clocks = <&osc>;
900 #clock-cells = <1>;
901 };
902 };
903
904 sysgpio: pinctrl@13040000 {
905 compatible = "starfive,jh7110-sys-pinctrl";
906 reg = <0x0 0x13040000 0x0 0x10000>;
907 clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
908 resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
909 interrupts = <86>;
910 interrupt-controller;
911 #interrupt-cells = <2>;
912 gpio-controller;
913 #gpio-cells = <2>;
914 };
915
916 watchdog@13070000 {
917 compatible = "starfive,jh7110-wdt";
918 reg = <0x0 0x13070000 0x0 0x10000>;
919 clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
920 <&syscrg JH7110_SYSCLK_WDT_CORE>;
921 clock-names = "apb", "core";
922 resets = <&syscrg JH7110_SYSRST_WDT_APB>,
923 <&syscrg JH7110_SYSRST_WDT_CORE>;
924 };
925
926 crypto: crypto@16000000 {
927 compatible = "starfive,jh7110-crypto";
928 reg = <0x0 0x16000000 0x0 0x4000>;
929 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
930 <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
931 clock-names = "hclk", "ahb";
932 interrupts = <28>;
933 resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
934 dmas = <&sdma 1 2>, <&sdma 0 2>;
935 dma-names = "tx", "rx";
936 };
937
938 sdma: dma-controller@16008000 {
939 compatible = "arm,pl080", "arm,primecell";
940 arm,primecell-periphid = <0x00041080>;
941 reg = <0x0 0x16008000 0x0 0x4000>;
942 interrupts = <29>;
943 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>;
944 clock-names = "apb_pclk";
945 resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
946 lli-bus-interface-ahb1;
947 mem-bus-interface-ahb1;
948 memcpy-burst-size = <256>;
949 memcpy-bus-width = <32>;
950 #dma-cells = <2>;
951 };
952
953 rng: rng@1600c000 {
954 compatible = "starfive,jh7110-trng";
955 reg = <0x0 0x1600C000 0x0 0x4000>;
956 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
957 <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
958 clock-names = "hclk", "ahb";
959 resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
960 interrupts = <30>;
961 };
962
963 mmc0: mmc@16010000 {
964 compatible = "starfive,jh7110-mmc";
965 reg = <0x0 0x16010000 0x0 0x10000>;
966 clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
967 <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
968 clock-names = "biu","ciu";
969 resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
970 reset-names = "reset";
971 interrupts = <74>;
972 fifo-depth = <32>;
973 fifo-watermark-aligned;
974 data-addr = <0>;
975 starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
976 status = "disabled";
977 };
978
979 mmc1: mmc@16020000 {
980 compatible = "starfive,jh7110-mmc";
981 reg = <0x0 0x16020000 0x0 0x10000>;
982 clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
983 <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
984 clock-names = "biu","ciu";
985 resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
986 reset-names = "reset";
987 interrupts = <75>;
988 fifo-depth = <32>;
989 fifo-watermark-aligned;
990 data-addr = <0>;
991 starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
992 status = "disabled";
993 };
994
995 gmac0: ethernet@16030000 {
996 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
997 reg = <0x0 0x16030000 0x0 0x10000>;
998 clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
999 <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
1000 <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
1001 <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
1002 <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
1003 clock-names = "stmmaceth", "pclk", "ptp_ref",
1004 "tx", "gtx";
1005 resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
1006 <&aoncrg JH7110_AONRST_GMAC0_AHB>;
1007 reset-names = "stmmaceth", "ahb";
1008 interrupts = <7>, <6>, <5>;
1009 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1010 rx-fifo-depth = <2048>;
1011 tx-fifo-depth = <2048>;
1012 snps,multicast-filter-bins = <64>;
1013 snps,perfect-filter-entries = <256>;
1014 snps,fixed-burst;
1015 snps,no-pbl-x8;
1016 snps,force_thresh_dma_mode;
1017 snps,axi-config = <&stmmac_axi_setup>;
1018 snps,tso;
1019 snps,en-tx-lpi-clockgating;
1020 snps,txpbl = <16>;
1021 snps,rxpbl = <16>;
1022 starfive,syscon = <&aon_syscon 0xc 0x12>;
1023 status = "disabled";
1024 };
1025
1026 gmac1: ethernet@16040000 {
1027 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
1028 reg = <0x0 0x16040000 0x0 0x10000>;
1029 clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
1030 <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
1031 <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
1032 <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
1033 <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
1034 clock-names = "stmmaceth", "pclk", "ptp_ref",
1035 "tx", "gtx";
1036 resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
1037 <&syscrg JH7110_SYSRST_GMAC1_AHB>;
1038 reset-names = "stmmaceth", "ahb";
1039 interrupts = <78>, <77>, <76>;
1040 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1041 rx-fifo-depth = <2048>;
1042 tx-fifo-depth = <2048>;
1043 snps,multicast-filter-bins = <64>;
1044 snps,perfect-filter-entries = <256>;
1045 snps,fixed-burst;
1046 snps,no-pbl-x8;
1047 snps,force_thresh_dma_mode;
1048 snps,axi-config = <&stmmac_axi_setup>;
1049 snps,tso;
1050 snps,en-tx-lpi-clockgating;
1051 snps,txpbl = <16>;
1052 snps,rxpbl = <16>;
1053 starfive,syscon = <&sys_syscon 0x90 0x2>;
1054 status = "disabled";
1055 };
1056
1057 dma: dma-controller@16050000 {
1058 compatible = "starfive,jh7110-axi-dma";
1059 reg = <0x0 0x16050000 0x0 0x10000>;
1060 clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
1061 <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
1062 clock-names = "core-clk", "cfgr-clk";
1063 resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
1064 <&stgcrg JH7110_STGRST_DMA1P_AHB>;
1065 interrupts = <73>;
1066 #dma-cells = <1>;
1067 dma-channels = <4>;
1068 snps,dma-masters = <1>;
1069 snps,data-width = <3>;
1070 snps,block-size = <65536 65536 65536 65536>;
1071 snps,priority = <0 1 2 3>;
1072 snps,axi-max-burst-len = <16>;
1073 };
1074
1075 aoncrg: clock-controller@17000000 {
1076 compatible = "starfive,jh7110-aoncrg";
1077 reg = <0x0 0x17000000 0x0 0x10000>;
1078 clocks = <&osc>, <&gmac0_rmii_refin>,
1079 <&gmac0_rgmii_rxin>,
1080 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
1081 <&syscrg JH7110_SYSCLK_APB_BUS>,
1082 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
1083 <&rtc_osc>;
1084 clock-names = "osc", "gmac0_rmii_refin",
1085 "gmac0_rgmii_rxin", "stg_axiahb",
1086 "apb_bus", "gmac0_gtxclk",
1087 "rtc_osc";
1088 #clock-cells = <1>;
1089 #reset-cells = <1>;
1090 };
1091
1092 aon_syscon: syscon@17010000 {
1093 compatible = "starfive,jh7110-aon-syscon", "syscon";
1094 reg = <0x0 0x17010000 0x0 0x1000>;
1095 #power-domain-cells = <1>;
1096 };
1097
1098 aongpio: pinctrl@17020000 {
1099 compatible = "starfive,jh7110-aon-pinctrl";
1100 reg = <0x0 0x17020000 0x0 0x10000>;
1101 resets = <&aoncrg JH7110_AONRST_IOMUX>;
1102 interrupts = <85>;
1103 interrupt-controller;
1104 #interrupt-cells = <2>;
1105 gpio-controller;
1106 #gpio-cells = <2>;
1107 };
1108
1109 pwrc: power-controller@17030000 {
1110 compatible = "starfive,jh7110-pmu";
1111 reg = <0x0 0x17030000 0x0 0x10000>;
1112 interrupts = <111>;
1113 #power-domain-cells = <1>;
1114 };
1115
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]1116 csi2rx: csi@19800000 {
1117 compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx";
1118 reg = <0x0 0x19800000 0x0 0x10000>;
1119 clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>,
1120 <&ispcrg JH7110_ISPCLK_VIN_APB>,
1121 <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF0>,
1122 <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF1>,
1123 <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF2>,
1124 <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF3>;
1125 clock-names = "sys_clk", "p_clk",
1126 "pixel_if0_clk", "pixel_if1_clk",
1127 "pixel_if2_clk", "pixel_if3_clk";
1128 resets = <&ispcrg JH7110_ISPRST_VIN_SYS>,
1129 <&ispcrg JH7110_ISPRST_VIN_APB>,
1130 <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF0>,
1131 <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF1>,
1132 <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF2>,
1133 <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF3>;
1134 reset-names = "sys", "reg_bank",
1135 "pixel_if0", "pixel_if1",
1136 "pixel_if2", "pixel_if3";
1137 phys = <&csi_phy>;
1138 phy-names = "dphy";
1139 status = "disabled";
1140 };
1141
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1142 ispcrg: clock-controller@19810000 {
1143 compatible = "starfive,jh7110-ispcrg";
1144 reg = <0x0 0x19810000 0x0 0x10000>;
1145 clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
1146 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
1147 <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
1148 <&dvp_clk>;
1149 clock-names = "isp_top_core", "isp_top_axi",
1150 "noc_bus_isp_axi", "dvp_clk";
1151 resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
1152 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
1153 <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
1154 #clock-cells = <1>;
1155 #reset-cells = <1>;
1156 power-domains = <&pwrc JH7110_PD_ISP>;
1157 };
1158
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame^]1159 csi_phy: phy@19820000 {
1160 compatible = "starfive,jh7110-dphy-rx";
1161 reg = <0x0 0x19820000 0x0 0x10000>;
1162 clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>,
1163 <&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>,
1164 <&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>;
1165 clock-names = "cfg", "ref", "tx";
1166 resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>,
1167 <&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>;
1168 power-domains = <&aon_syscon JH7110_AON_PD_DPHY_RX>;
1169 #phy-cells = <0>;
1170 };
1171
1172 camss: isp@19840000 {
1173 compatible = "starfive,jh7110-camss";
1174 reg = <0x0 0x19840000 0x0 0x10000>,
1175 <0x0 0x19870000 0x0 0x30000>;
1176 reg-names = "syscon", "isp";
1177 clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
1178 <&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>,
1179 <&ispcrg JH7110_ISPCLK_DVP_INV>,
1180 <&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>,
1181 <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>,
1182 <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
1183 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>;
1184 clock-names = "apb_func", "wrapper_clk_c", "dvp_inv",
1185 "axiwr", "mipi_rx0_pxl", "ispcore_2x",
1186 "isp_axi";
1187 resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>,
1188 <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>,
1189 <&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>,
1190 <&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>,
1191 <&syscrg JH7110_SYSRST_ISP_TOP>,
1192 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>;
1193 reset-names = "wrapper_p", "wrapper_c", "axird",
1194 "axiwr", "isp_top_n", "isp_top_axi";
1195 power-domains = <&pwrc JH7110_PD_ISP>;
1196 interrupts = <92>, <87>, <90>, <88>;
1197 status = "disabled";
1198 };
1199
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1200 voutcrg: clock-controller@295c0000 {
1201 compatible = "starfive,jh7110-voutcrg";
1202 reg = <0x0 0x295c0000 0x0 0x10000>;
1203 clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
1204 <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
1205 <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
1206 <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
1207 <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
1208 <&hdmitx0_pixelclk>;
1209 clock-names = "vout_src", "vout_top_ahb",
1210 "vout_top_axi", "vout_top_hdmitx0_mclk",
1211 "i2stx0_bclk", "hdmitx0_pixelclk";
1212 resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
1213 #clock-cells = <1>;
1214 #reset-cells = <1>;
1215 power-domains = <&pwrc JH7110_PD_VOUT>;
1216 };
1217 };
1218};