blob: ea83671988a3efd8250a9979015cb8be2810133e [file] [log] [blame]
John Otkend4024bb2007-07-26 17:49:11 +02001/*
2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2005-2007
6 * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26#include <common.h>
27#include <command.h>
28#include <asm/processor.h>
29#include <asm/io.h>
30#include <spi.h>
31#include <asm/gpio.h>
32
33extern int lcd_init(void);
34
35/*
36 * board_early_init_f
37 */
38int board_early_init_f(void)
39{
40 lcd_init();
41
42 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
43 mtdcr(uicer, 0x00000000); /* disable all ints */
44 mtdcr(uiccr, 0x00000000);
45 mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
46 mtdcr(uictr, 0x00000000); /* set int trigger levels */
47 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
48 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
49
50 mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
51 mtebc(pb3cr, CFG_EBC_PB3CR);
52
Stefan Roese779e9752007-08-14 14:44:41 +020053 /*
54 * Configure CPC0_PCI to enable PerWE as output
55 * and enable the internal PCI arbiter
56 */
57 mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
58
John Otkend4024bb2007-07-26 17:49:11 +020059 return 0;
60}
61
62/*
63 * Check Board Identity:
64 */
65int checkboard(void)
66{
67 char *s = getenv("serial#");
68
69 puts("Board: Taihu - AMCC PPC405EP Evaluation Board");
70
71 if (s != NULL) {
72 puts(", serial# ");
73 puts(s);
74 }
75 putc('\n');
76
77 return 0;
78}
79
80/*************************************************************************
81 * long int initdram
82 *
83 ************************************************************************/
84long int initdram(int board)
85{
86 return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
87}
88
89static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
90{
91 char stat;
92 int i;
93
94 stat = in_8((u8 *) CPLD_REG0_ADDR);
95 printf("SW2 status: ");
96 for (i=0; i<4; i++) /* 4-position */
97 printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off");
98 printf("\n");
99 return 0;
100}
101
102U_BOOT_CMD (
103 sw2_stat, 1, 1, do_sw_stat,
104 "sw2_stat - show status of switch 2\n",
105 NULL
106 );
107
108static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
109{
110 int led_no;
111
112 if (argc != 3) {
113 printf("%s", cmd_tp->usage);
114 return -1;
115 }
116
117 led_no = simple_strtoul(argv[1], NULL, 16);
118 if (led_no != 1 && led_no != 2) {
119 printf("%s", cmd_tp->usage);
120 return -1;
121 }
122
123 if (strcmp(argv[2],"off") == 0x0) {
124 if (led_no == 1)
125 gpio_write_bit(30, 1);
126 else
127 gpio_write_bit(31, 1);
128 } else if (strcmp(argv[2],"on") == 0x0) {
129 if (led_no == 1)
130 gpio_write_bit(30, 0);
131 else
132 gpio_write_bit(31, 0);
133 } else {
134 printf("%s", cmd_tp->usage);
135 return -1;
136 }
137
138 return 0;
139}
140
141U_BOOT_CMD (
142 led_ctl, 3, 1, do_led_ctl,
143 "led_ctl - make led 1 or 2 on or off\n",
144 "<led_no> <on/off> - make led <led_no> on/off,\n"
145 "\tled_no is 1 or 2\t"
146 );
147
148#define SPI_CS_GPIO0 0
149#define SPI_SCLK_GPIO14 14
150#define SPI_DIN_GPIO15 15
151#define SPI_DOUT_GPIO16 16
152
153void spi_scl(int bit)
154{
155 gpio_write_bit(SPI_SCLK_GPIO14, bit);
156}
157
158void spi_sda(int bit)
159{
160 gpio_write_bit(SPI_DOUT_GPIO16, bit);
161}
162
163unsigned char spi_read(void)
164{
165 return (unsigned char)gpio_read_out_bit(SPI_DIN_GPIO15);
166}
167
168void taihu_spi_chipsel(int cs)
169{
170 gpio_write_bit(SPI_CS_GPIO0, cs);
171}
172
173spi_chipsel_type spi_chipsel[]= {
174 taihu_spi_chipsel
175};
176
177int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
178
179#ifdef CONFIG_PCI
180static unsigned char int_lines[32] = {
181 29, 30, 27, 28, 29, 30, 25, 27,
182 29, 30, 27, 28, 29, 30, 27, 28,
183 29, 30, 27, 28, 29, 30, 27, 28,
184 29, 30, 27, 28, 29, 30, 27, 28};
185
186static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
187{
188 unsigned char int_line = int_lines[PCI_DEV(dev) & 31];
189
190 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
191}
192
193int pci_pre_init(struct pci_controller *hose)
194{
195 hose->fixup_irq = taihu_pci_fixup_irq;
196 return 1;
197}
198#endif /* CONFIG_PCI */
199
200#ifdef CFG_DRAM_TEST
201int testdram(void)
202{
203 unsigned long *mem = (unsigned long *)0;
204 const unsigned long kend = (1024 / sizeof(unsigned long));
205 unsigned long k, n;
206 unsigned long msr;
207 unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024;
208
209 msr = mfmsr();
210 mtmsr(msr & ~(MSR_EE));
211
212 for (k = 0; k < total_kbytes ;
213 ++k, mem += (1024 / sizeof(unsigned long))) {
214 if ((k & 1023) == 0)
215 printf("%3d MB\r", k / 1024);
216
217 memset(mem, 0xaaaaaaaa, 1024);
218 for (n = 0; n < kend; ++n) {
219 if (mem[n] != 0xaaaaaaaa) {
220 printf("SDRAM test fails at: %08x\n",
221 (uint) & mem[n]);
222 return 1;
223 }
224 }
225
226 memset(mem, 0x55555555, 1024);
227 for (n = 0; n < kend; ++n) {
228 if (mem[n] != 0x55555555) {
229 printf("SDRAM test fails at: %08x\n",
230 (uint) & mem[n]);
231 return 1;
232 }
233 }
234 }
235 printf("SDRAM test passes\n");
236 mtmsr(msr);
237
238 return 0;
239}
240#endif /* CFG_DRAM_TEST */