blob: b566705c9d974b672e937bbcc8e6e1c46002cd53 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00002/*
Simon Glass2b81e8a2015-11-29 13:17:46 -07003 * PCI autoconfiguration library (legacy version, do not change)
wdenkc6097192002-11-03 00:24:07 +00004 *
5 * Author: Matt Porter <mporter@mvista.com>
6 *
7 * Copyright 2000 MontaVista Software Inc.
wdenkc6097192002-11-03 00:24:07 +00008 */
9
10#include <common.h>
Simon Glass4a2708a2015-01-14 21:37:04 -070011#include <errno.h>
wdenkc6097192002-11-03 00:24:07 +000012#include <pci.h>
13
Simon Glass2b81e8a2015-11-29 13:17:46 -070014/*
15 * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
16 * and change pci_auto.c.
17 */
18
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020019/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
20#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
21#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
Gary Jennejohn81b73de2007-08-31 15:21:46 +020022#endif
23
wdenkc6097192002-11-03 00:24:07 +000024/*
25 *
26 */
27
wdenkc6097192002-11-03 00:24:07 +000028void pciauto_setup_device(struct pci_controller *hose,
29 pci_dev_t dev, int bars_num,
30 struct pci_region *mem,
Kumar Galaa1790122006-01-11 13:24:15 -060031 struct pci_region *prefetch,
wdenkc6097192002-11-03 00:24:07 +000032 struct pci_region *io)
33{
Kumar Galacf5787f2012-09-19 04:47:36 +000034 u32 bar_response;
Kumar Gala30e76d52008-10-21 08:36:08 -050035 pci_size_t bar_size;
Andrew Sharpaf778c62012-08-01 12:27:16 +000036 u16 cmdstat = 0;
wdenkc6097192002-11-03 00:24:07 +000037 int bar, bar_nr = 0;
Simon Glass53292ad2015-07-31 09:31:34 -060038#ifndef CONFIG_PCI_ENUM_ONLY
Bin Meng6c896632015-07-08 13:06:40 +080039 u8 header_type;
40 int rom_addr;
Andrew Sharp69fd2d32012-08-29 14:16:32 +000041 pci_addr_t bar_value;
42 struct pci_region *bar_res;
wdenkc6097192002-11-03 00:24:07 +000043 int found_mem64 = 0;
Andrew Sharp69fd2d32012-08-29 14:16:32 +000044#endif
Bin Mengcdf9f082015-10-01 00:35:59 -070045 u16 class;
wdenkc6097192002-11-03 00:24:07 +000046
Andrew Sharpaf778c62012-08-01 12:27:16 +000047 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
wdenkc6097192002-11-03 00:24:07 +000048 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
49
Andrew Sharpcb2bf932012-08-29 14:16:29 +000050 for (bar = PCI_BASE_ADDRESS_0;
51 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
wdenkc6097192002-11-03 00:24:07 +000052 /* Tickle the BAR and get the response */
Andrew Sharp69fd2d32012-08-29 14:16:32 +000053#ifndef CONFIG_PCI_ENUM_ONLY
wdenkc6097192002-11-03 00:24:07 +000054 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
Andrew Sharp69fd2d32012-08-29 14:16:32 +000055#endif
wdenkc6097192002-11-03 00:24:07 +000056 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
57
58 /* If BAR is not implemented go to the next BAR */
59 if (!bar_response)
60 continue;
61
Andrew Sharp69fd2d32012-08-29 14:16:32 +000062#ifndef CONFIG_PCI_ENUM_ONLY
wdenkc6097192002-11-03 00:24:07 +000063 found_mem64 = 0;
Andrew Sharp69fd2d32012-08-29 14:16:32 +000064#endif
wdenkc6097192002-11-03 00:24:07 +000065
66 /* Check the BAR type and set our address mask */
wdenk3c74e322004-02-22 23:46:08 +000067 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
Jin Zhengxiong-R64188bd22c2b2006-06-27 18:12:02 +080068 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
69 & 0xffff) + 1;
Andrew Sharp69fd2d32012-08-29 14:16:32 +000070#ifndef CONFIG_PCI_ENUM_ONLY
wdenkc6097192002-11-03 00:24:07 +000071 bar_res = io;
Andrew Sharp69fd2d32012-08-29 14:16:32 +000072#endif
wdenkc6097192002-11-03 00:24:07 +000073
Simon Glassda4b1592015-07-31 09:31:33 -060074 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
75 bar_nr, (unsigned long long)bar_size);
wdenk3c74e322004-02-22 23:46:08 +000076 } else {
Andrew Sharpcb2bf932012-08-29 14:16:29 +000077 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
Kumar Gala30e76d52008-10-21 08:36:08 -050078 PCI_BASE_ADDRESS_MEM_TYPE_64) {
79 u32 bar_response_upper;
80 u64 bar64;
Andrew Sharp69fd2d32012-08-29 14:16:32 +000081
82#ifndef CONFIG_PCI_ENUM_ONLY
Andrew Sharpcb2bf932012-08-29 14:16:29 +000083 pci_hose_write_config_dword(hose, dev, bar + 4,
84 0xffffffff);
Andrew Sharp69fd2d32012-08-29 14:16:32 +000085#endif
Andrew Sharpcb2bf932012-08-29 14:16:29 +000086 pci_hose_read_config_dword(hose, dev, bar + 4,
87 &bar_response_upper);
wdenkc6097192002-11-03 00:24:07 +000088
Kumar Gala30e76d52008-10-21 08:36:08 -050089 bar64 = ((u64)bar_response_upper << 32) | bar_response;
90
91 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
Andrew Sharp69fd2d32012-08-29 14:16:32 +000092#ifndef CONFIG_PCI_ENUM_ONLY
Kumar Gala30e76d52008-10-21 08:36:08 -050093 found_mem64 = 1;
Andrew Sharp69fd2d32012-08-29 14:16:32 +000094#endif
Kumar Gala30e76d52008-10-21 08:36:08 -050095 } else {
96 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
97 }
Andrew Sharp69fd2d32012-08-29 14:16:32 +000098#ifndef CONFIG_PCI_ENUM_ONLY
Kumar Galaa1790122006-01-11 13:24:15 -060099 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
100 bar_res = prefetch;
101 else
102 bar_res = mem;
wdenkc6097192002-11-03 00:24:07 +0000103
Simon Glass4bad2e72015-07-27 15:47:18 -0600104 debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
105 bar_nr, bar_res == prefetch ? "Prf" : "Mem",
106 (unsigned long long)bar_size);
Phil Sutter11131462015-12-25 14:41:17 +0100107#endif
wdenkc6097192002-11-03 00:24:07 +0000108 }
109
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000110#ifndef CONFIG_PCI_ENUM_ONLY
Tuomas Tynkkynend71975a2018-05-14 19:38:13 +0300111 if (pciauto_region_allocate(bar_res, bar_size,
112 &bar_value, found_mem64) == 0) {
wdenkc6097192002-11-03 00:24:07 +0000113 /* Write it out and update our limit */
Kumar Gala30e76d52008-10-21 08:36:08 -0500114 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
wdenkc6097192002-11-03 00:24:07 +0000115
wdenk3c74e322004-02-22 23:46:08 +0000116 if (found_mem64) {
wdenkc6097192002-11-03 00:24:07 +0000117 bar += 4;
Kumar Gala30e76d52008-10-21 08:36:08 -0500118#ifdef CONFIG_SYS_PCI_64BIT
119 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
120#else
121 /*
122 * If we are a 64-bit decoder then increment to the
123 * upper 32 bits of the bar and force it to locate
124 * in the lower 4GB of memory.
125 */
wdenkc6097192002-11-03 00:24:07 +0000126 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
Kumar Gala30e76d52008-10-21 08:36:08 -0500127#endif
wdenkc6097192002-11-03 00:24:07 +0000128 }
129
wdenkc6097192002-11-03 00:24:07 +0000130 }
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000131#endif
132 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
133 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
wdenkc6097192002-11-03 00:24:07 +0000134
Simon Glassda4b1592015-07-31 09:31:33 -0600135 debug("\n");
wdenkc6097192002-11-03 00:24:07 +0000136
137 bar_nr++;
138 }
139
Simon Glass53292ad2015-07-31 09:31:34 -0600140#ifndef CONFIG_PCI_ENUM_ONLY
Bin Meng6c896632015-07-08 13:06:40 +0800141 /* Configure the expansion ROM address */
142 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
Bin Meng74454352015-10-07 02:13:18 -0700143 header_type &= 0x7f;
Bin Meng6c896632015-07-08 13:06:40 +0800144 if (header_type != PCI_HEADER_TYPE_CARDBUS) {
145 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
146 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
147 pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
148 pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
149 if (bar_response) {
150 bar_size = -(bar_response & ~1);
Simon Glassda4b1592015-07-31 09:31:33 -0600151 debug("PCI Autoconfig: ROM, size=%#x, ",
152 (unsigned int)bar_size);
Bin Meng6c896632015-07-08 13:06:40 +0800153 if (pciauto_region_allocate(mem, bar_size,
Tuomas Tynkkynend71975a2018-05-14 19:38:13 +0300154 &bar_value, false) == 0) {
Bin Meng6c896632015-07-08 13:06:40 +0800155 pci_hose_write_config_dword(hose, dev, rom_addr,
156 bar_value);
157 }
158 cmdstat |= PCI_COMMAND_MEMORY;
Simon Glassda4b1592015-07-31 09:31:33 -0600159 debug("\n");
Bin Meng6c896632015-07-08 13:06:40 +0800160 }
161 }
Simon Glass53292ad2015-07-31 09:31:34 -0600162#endif
Bin Meng6c896632015-07-08 13:06:40 +0800163
Bin Mengcdf9f082015-10-01 00:35:59 -0700164 /* PCI_COMMAND_IO must be set for VGA device */
165 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
166 if (class == PCI_CLASS_DISPLAY_VGA)
167 cmdstat |= PCI_COMMAND_IO;
168
Andrew Sharpaf778c62012-08-01 12:27:16 +0000169 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
Gary Jennejohn81b73de2007-08-31 15:21:46 +0200170 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
wdenkc6097192002-11-03 00:24:07 +0000172 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
173}
174
Ed Swarthoutba5feb12007-07-11 14:51:48 -0500175void pciauto_prescan_setup_bridge(struct pci_controller *hose,
wdenkc6097192002-11-03 00:24:07 +0000176 pci_dev_t dev, int sub_bus)
177{
Bin Mengd11d9ef2015-07-19 00:20:06 +0800178 struct pci_region *pci_mem;
179 struct pci_region *pci_prefetch;
180 struct pci_region *pci_io;
David Feng6eefd522015-02-02 16:53:13 +0800181 u16 cmdstat, prefechable_64;
wdenkc6097192002-11-03 00:24:07 +0000182
Bin Mengd11d9ef2015-07-19 00:20:06 +0800183 pci_mem = hose->pci_mem;
184 pci_prefetch = hose->pci_prefetch;
185 pci_io = hose->pci_io;
Bin Mengd11d9ef2015-07-19 00:20:06 +0800186
Andrew Sharpaf778c62012-08-01 12:27:16 +0000187 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
David Feng6eefd522015-02-02 16:53:13 +0800188 pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
189 &prefechable_64);
190 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
wdenkc6097192002-11-03 00:24:07 +0000191
192 /* Configure bus number registers */
Ed Swarthoute8b85f32007-07-11 14:52:08 -0500193 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
194 PCI_BUS(dev) - hose->first_busno);
195 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
196 sub_bus - hose->first_busno);
wdenkc6097192002-11-03 00:24:07 +0000197 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
198
wdenk3c74e322004-02-22 23:46:08 +0000199 if (pci_mem) {
wdenkc6097192002-11-03 00:24:07 +0000200 /* Round memory allocator to 1MB boundary */
201 pciauto_region_align(pci_mem, 0x100000);
202
203 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
204 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
205 (pci_mem->bus_lower & 0xfff00000) >> 16);
206
207 cmdstat |= PCI_COMMAND_MEMORY;
208 }
209
Kumar Galaa1790122006-01-11 13:24:15 -0600210 if (pci_prefetch) {
211 /* Round memory allocator to 1MB boundary */
212 pciauto_region_align(pci_prefetch, 0x100000);
213
214 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
215 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
216 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
David Feng6eefd522015-02-02 16:53:13 +0800217 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
218#ifdef CONFIG_SYS_PCI_64BIT
219 pci_hose_write_config_dword(hose, dev,
220 PCI_PREF_BASE_UPPER32,
221 pci_prefetch->bus_lower >> 32);
222#else
223 pci_hose_write_config_dword(hose, dev,
224 PCI_PREF_BASE_UPPER32,
225 0x0);
226#endif
Kumar Galaa1790122006-01-11 13:24:15 -0600227
228 cmdstat |= PCI_COMMAND_MEMORY;
229 } else {
230 /* We don't support prefetchable memory for now, so disable */
231 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
Matthew McClintocka4e11552006-06-28 10:44:23 -0500232 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
David Feng6eefd522015-02-02 16:53:13 +0800233 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
234 pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
235 pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
236 }
Kumar Galaa1790122006-01-11 13:24:15 -0600237 }
238
wdenk3c74e322004-02-22 23:46:08 +0000239 if (pci_io) {
wdenkc6097192002-11-03 00:24:07 +0000240 /* Round I/O allocator to 4KB boundary */
241 pciauto_region_align(pci_io, 0x1000);
242
243 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
244 (pci_io->bus_lower & 0x0000f000) >> 8);
245 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
246 (pci_io->bus_lower & 0xffff0000) >> 16);
247
248 cmdstat |= PCI_COMMAND_IO;
249 }
250
wdenkc6097192002-11-03 00:24:07 +0000251 /* Enable memory and I/O accesses, enable bus master */
Andrew Sharpaf778c62012-08-01 12:27:16 +0000252 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
253 cmdstat | PCI_COMMAND_MASTER);
wdenkc6097192002-11-03 00:24:07 +0000254}
255
Ed Swarthoutba5feb12007-07-11 14:51:48 -0500256void pciauto_postscan_setup_bridge(struct pci_controller *hose,
wdenkc6097192002-11-03 00:24:07 +0000257 pci_dev_t dev, int sub_bus)
258{
Bin Mengd11d9ef2015-07-19 00:20:06 +0800259 struct pci_region *pci_mem;
260 struct pci_region *pci_prefetch;
261 struct pci_region *pci_io;
262
Bin Mengd11d9ef2015-07-19 00:20:06 +0800263 pci_mem = hose->pci_mem;
264 pci_prefetch = hose->pci_prefetch;
265 pci_io = hose->pci_io;
wdenkc6097192002-11-03 00:24:07 +0000266
267 /* Configure bus number registers */
Ed Swarthoute8b85f32007-07-11 14:52:08 -0500268 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
269 sub_bus - hose->first_busno);
wdenkc6097192002-11-03 00:24:07 +0000270
wdenk3c74e322004-02-22 23:46:08 +0000271 if (pci_mem) {
wdenkc6097192002-11-03 00:24:07 +0000272 /* Round memory allocator to 1MB boundary */
273 pciauto_region_align(pci_mem, 0x100000);
274
275 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000276 (pci_mem->bus_lower - 1) >> 16);
wdenkc6097192002-11-03 00:24:07 +0000277 }
278
Kumar Galaa1790122006-01-11 13:24:15 -0600279 if (pci_prefetch) {
David Feng6eefd522015-02-02 16:53:13 +0800280 u16 prefechable_64;
281
282 pci_hose_read_config_word(hose, dev,
283 PCI_PREF_MEMORY_LIMIT,
284 &prefechable_64);
285 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
286
Kumar Galaa1790122006-01-11 13:24:15 -0600287 /* Round memory allocator to 1MB boundary */
288 pciauto_region_align(pci_prefetch, 0x100000);
289
290 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000291 (pci_prefetch->bus_lower - 1) >> 16);
David Feng6eefd522015-02-02 16:53:13 +0800292 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
293#ifdef CONFIG_SYS_PCI_64BIT
294 pci_hose_write_config_dword(hose, dev,
295 PCI_PREF_LIMIT_UPPER32,
296 (pci_prefetch->bus_lower - 1) >> 32);
297#else
298 pci_hose_write_config_dword(hose, dev,
299 PCI_PREF_LIMIT_UPPER32,
300 0x0);
301#endif
Kumar Galaa1790122006-01-11 13:24:15 -0600302 }
303
wdenk3c74e322004-02-22 23:46:08 +0000304 if (pci_io) {
wdenkc6097192002-11-03 00:24:07 +0000305 /* Round I/O allocator to 4KB boundary */
306 pciauto_region_align(pci_io, 0x1000);
307
308 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000309 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
wdenkc6097192002-11-03 00:24:07 +0000310 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000311 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
wdenkc6097192002-11-03 00:24:07 +0000312 }
313}
314
wdenkc6097192002-11-03 00:24:07 +0000315
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000316/*
317 * HJF: Changed this to return int. I think this is required
wdenkc7de8292002-11-19 11:04:11 +0000318 * to get the correct result when scanning bridges
319 */
320int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
wdenkc6097192002-11-03 00:24:07 +0000321{
Bin Mengd11d9ef2015-07-19 00:20:06 +0800322 struct pci_region *pci_mem;
323 struct pci_region *pci_prefetch;
324 struct pci_region *pci_io;
wdenkc7de8292002-11-19 11:04:11 +0000325 unsigned int sub_bus = PCI_BUS(dev);
wdenkc6097192002-11-03 00:24:07 +0000326 unsigned short class;
wdenk5653fc32004-02-08 22:55:38 +0000327 int n;
wdenkc6097192002-11-03 00:24:07 +0000328
Bin Mengd11d9ef2015-07-19 00:20:06 +0800329 pci_mem = hose->pci_mem;
330 pci_prefetch = hose->pci_prefetch;
331 pci_io = hose->pci_io;
Bin Mengd11d9ef2015-07-19 00:20:06 +0800332
wdenkc6097192002-11-03 00:24:07 +0000333 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
334
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000335 switch (class) {
wdenkc6097192002-11-03 00:24:07 +0000336 case PCI_CLASS_BRIDGE_PCI:
Simon Glassda4b1592015-07-31 09:31:33 -0600337 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
338 PCI_DEV(dev));
Simon Glassff3e0772015-03-05 12:25:25 -0700339
Bin Mengd11d9ef2015-07-19 00:20:06 +0800340 pciauto_setup_device(hose, dev, 2, pci_mem,
341 pci_prefetch, pci_io);
wdenkc6097192002-11-03 00:24:07 +0000342
wdenk3c74e322004-02-22 23:46:08 +0000343 /* Passing in current_busno allows for sibling P2P bridges */
Simon Glassff3e0772015-03-05 12:25:25 -0700344 hose->current_busno++;
wdenk5653fc32004-02-08 22:55:38 +0000345 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
wdenkcd37d9e2004-02-10 00:03:41 +0000346 /*
wdenk3c74e322004-02-22 23:46:08 +0000347 * need to figure out if this is a subordinate bridge on the bus
wdenk5653fc32004-02-08 22:55:38 +0000348 * to be able to properly set the pri/sec/sub bridge registers.
349 */
350 n = pci_hose_scan_bus(hose, hose->current_busno);
wdenk8bde7f72003-06-27 21:31:46 +0000351
wdenk3c74e322004-02-22 23:46:08 +0000352 /* figure out the deepest we've gone for this leg */
Masahiro Yamadab4141192014-11-07 03:03:31 +0900353 sub_bus = max((unsigned int)n, sub_bus);
wdenkdb2f721f2003-03-06 00:58:30 +0000354 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
wdenk5653fc32004-02-08 22:55:38 +0000355
wdenkdb2f721f2003-03-06 00:58:30 +0000356 sub_bus = hose->current_busno;
wdenkc6097192002-11-03 00:24:07 +0000357 break;
358
wdenk1cb8e982003-03-06 21:55:29 +0000359 case PCI_CLASS_BRIDGE_CARDBUS:
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000360 /*
361 * just do a minimal setup of the bridge,
362 * let the OS take care of the rest
363 */
Bin Mengd11d9ef2015-07-19 00:20:06 +0800364 pciauto_setup_device(hose, dev, 0, pci_mem,
365 pci_prefetch, pci_io);
wdenk1cb8e982003-03-06 21:55:29 +0000366
Simon Glassda4b1592015-07-31 09:31:33 -0600367 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
368 PCI_DEV(dev));
wdenk1cb8e982003-03-06 21:55:29 +0000369
370 hose->current_busno++;
371 break;
372
TsiChung Liewf33fca22008-03-30 01:19:06 -0500373#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
wdenke0ac62d2003-08-17 18:55:18 +0000374 case PCI_CLASS_BRIDGE_OTHER:
Simon Glassda4b1592015-07-31 09:31:33 -0600375 debug("PCI Autoconfig: Skipping bridge device %d\n",
376 PCI_DEV(dev));
wdenke0ac62d2003-08-17 18:55:18 +0000377 break;
378#endif
Mario Six904c47f2019-01-21 09:17:38 +0100379#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
380 !defined(CONFIG_TARGET_CADDY2)
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200381 case PCI_CLASS_BRIDGE_OTHER:
382 /*
383 * The host/PCI bridge 1 seems broken in 8349 - it presents
384 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
385 * device claiming resources io/mem/irq.. we only allow for
386 * the PIMMR window to be allocated (BAR0 - 1MB size)
387 */
Simon Glassda4b1592015-07-31 09:31:33 -0600388 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000389 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
390 hose->pci_prefetch, hose->pci_io);
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200391 break;
392#endif
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000393
394 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
Simon Glassda4b1592015-07-31 09:31:33 -0600395 debug("PCI AutoConfig: Found PowerPC device\n");
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000396
wdenkc6097192002-11-03 00:24:07 +0000397 default:
Bin Mengd11d9ef2015-07-19 00:20:06 +0800398 pciauto_setup_device(hose, dev, 6, pci_mem,
399 pci_prefetch, pci_io);
wdenkc6097192002-11-03 00:24:07 +0000400 break;
401 }
wdenkc7de8292002-11-19 11:04:11 +0000402
403 return sub_bus;
wdenkc6097192002-11-03 00:24:07 +0000404}