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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Bin Meng02c57ab2016-10-09 04:14:11 -07002/*
3 * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
Bin Meng02c57ab2016-10-09 04:14:11 -07004 */
5
6#include <common.h>
7#include <dm.h>
Simon Glass6c74ee32020-07-02 21:12:36 -06008#include <log.h>
Bin Meng02c57ab2016-10-09 04:14:11 -07009#include <pci.h>
10#include <vbe.h>
Simon Glass6c74ee32020-07-02 21:12:36 -060011#include <video.h>
12#include <asm/mtrr.h>
Bin Meng02c57ab2016-10-09 04:14:11 -070013
14static int vesa_video_probe(struct udevice *dev)
15{
Simon Glass6c74ee32020-07-02 21:12:36 -060016 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
17 ulong fbbase;
18 int ret;
19
20 ret = vbe_setup_video(dev, NULL);
21 if (ret)
22 return log_ret(ret);
23
24 /* Use write-combining for the graphics memory, 256MB */
25 fbbase = IS_ENABLED(CONFIG_VIDEO_COPY) ? plat->copy_base : plat->base;
26 mtrr_add_request(MTRR_TYPE_WRCOMB, fbbase, 256 << 20);
27 mtrr_commit(true);
28
29 return 0;
30}
31
32static int vesa_video_bind(struct udevice *dev)
33{
34 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
35
36 /* Set the maximum supported resolution */
37 uc_plat->size = 2560 * 1600 * 4;
38 log_debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
39
40 return 0;
Bin Meng02c57ab2016-10-09 04:14:11 -070041}
42
43static const struct udevice_id vesa_video_ids[] = {
44 { .compatible = "vesa-fb" },
45 { }
46};
47
48U_BOOT_DRIVER(vesa_video) = {
49 .name = "vesa_video",
50 .id = UCLASS_VIDEO,
51 .of_match = vesa_video_ids,
Simon Glass6c74ee32020-07-02 21:12:36 -060052 .bind = vesa_video_bind,
Bin Meng02c57ab2016-10-09 04:14:11 -070053 .probe = vesa_video_probe,
54};
55
56static struct pci_device_id vesa_video_supported[] = {
57 { PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, ~0) },
58 { },
59};
60
61U_BOOT_PCI_DEVICE(vesa_video, vesa_video_supported);