| Shaohui Xie | 02b5d2e | 2015-11-11 17:58:37 +0800 | [diff] [blame] | 1 | Overview |
| 2 | -------- |
| 3 | The LS1043A Development System (QDS) is a high-performance computing, |
| 4 | evaluation, and development platform that supports the QorIQ LS1043A |
| 5 | LayerScape Architecture processor. The LS1043AQDS provides SW development |
| 6 | platform for the Freescale LS1043A processor series, with a complete |
| 7 | debugging environment. |
| 8 | |
| 9 | LS1043A SoC Overview |
| 10 | -------------------- |
| Prabhakar Kushwaha | ddd8a08 | 2016-06-03 18:41:30 +0530 | [diff] [blame] | 11 | Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A |
| 12 | SoC overview. |
| Shaohui Xie | 02b5d2e | 2015-11-11 17:58:37 +0800 | [diff] [blame] | 13 | |
| 14 | LS1043AQDS board Overview |
| 15 | ----------------------- |
| 16 | - SERDES Connections, 4 lanes supporting: |
| 17 | - PCI Express - 3.0 |
| 18 | - SGMII, SGMII 2.5 |
| 19 | - QSGMII |
| 20 | - SATA 3.0 |
| Vladimir Oltean | 77b11f7 | 2021-09-18 15:32:34 +0300 | [diff] [blame] | 21 | - 10GBase-R |
| Shaohui Xie | 02b5d2e | 2015-11-11 17:58:37 +0800 | [diff] [blame] | 22 | - DDR Controller |
| 23 | - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s |
| 24 | -IFC/Local Bus |
| 25 | - One in-socket 128 MB NOR flash 16-bit data bus |
| 26 | - One 512 MB NAND flash with ECC support |
| 27 | - PromJet Port |
| 28 | - FPGA connection |
| 29 | - USB 3.0 |
| 30 | - Three high speed USB 3.0 ports |
| 31 | - First USB 3.0 port configured as Host with Type-A connector |
| 32 | - The other two USB 3.0 ports configured as OTG with micro-AB connector |
| 33 | - SDHC port connects directly to an adapter card slot, featuring: |
| 34 | - Optional clock feedback paths, and optional high-speed voltage translation assistance |
| 35 | - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC |
| 36 | - eMMC memory devices |
| 37 | - DSPI: Onboard support for three SPI flash memory devices |
| 38 | - 4 I2C controllers |
| 39 | - One SATA onboard connectors |
| 40 | - UART |
| 41 | - Two 4-pin serial ports at up to 115.2 Kbit/s |
| 42 | - Two DB9 D-Type connectors supporting one Serial port each |
| 43 | - ARM JTAG support |
| 44 | |
| 45 | Memory map from core's view |
| 46 | ---------------------------- |
| 47 | Start Address End Address Description Size |
| 48 | 0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB |
| 49 | 0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB |
| 50 | 0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB |
| 51 | 0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB |
| 52 | 0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB |
| 53 | 0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB |
| 54 | 0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB |
| 55 | 0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB |
| 56 | 0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB |
| 57 | |
| 58 | Booting Options |
| 59 | --------------- |
| 60 | a) Promjet Boot |
| 61 | b) NOR boot |
| 62 | c) NAND boot |
| 63 | d) SD boot |
| Qianyu Gong | b0f20ca | 2016-01-25 15:16:07 +0800 | [diff] [blame] | 64 | e) QSPI boot |