| Fabio Estevam | d5b7177 | 2018-06-29 15:19:11 -0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2018 Technexion Ltd. |
| 4 | * |
| 5 | * Author: Richard Hu <richard.hu@technexion.com> |
| 6 | */ |
| 7 | |
| 8 | #include <asm/arch/imx-regs.h> |
| 9 | #include <asm/arch/crm_regs.h> |
| 10 | #include <asm/arch/sys_proto.h> |
| 11 | #include <asm/arch-mx7/mx7-ddr.h> |
| 12 | #include <asm/gpio.h> |
| 13 | #include <spl.h> |
| 14 | |
| 15 | #if defined(CONFIG_SPL_BUILD) |
| 16 | static struct ddrc ddrc_regs_val = { |
| 17 | .mstr = 0x01040001, |
| 18 | .rfshtmg = 0x00400046, |
| 19 | .init1 = 0x00690000, |
| 20 | .init0 = 0x00020083, |
| 21 | .init3 = 0x09300004, |
| 22 | .init4 = 0x04080000, |
| 23 | .init5 = 0x00100004, |
| 24 | .rankctl = 0x0000033F, |
| 25 | .dramtmg0 = 0x09081109, |
| 26 | .dramtmg1 = 0x0007020d, |
| 27 | .dramtmg2 = 0x03040407, |
| 28 | .dramtmg3 = 0x00002006, |
| 29 | .dramtmg4 = 0x04020205, |
| 30 | .dramtmg5 = 0x03030202, |
| 31 | .dramtmg8 = 0x00000803, |
| 32 | .zqctl0 = 0x00800020, |
| 33 | .dfitmg0 = 0x02098204, |
| 34 | .dfitmg1 = 0x00030303, |
| 35 | .dfiupd0 = 0x80400003, |
| 36 | .dfiupd1 = 0x00100020, |
| 37 | .dfiupd2 = 0x80100004, |
| 38 | .addrmap4 = 0x00000F0F, |
| 39 | .odtcfg = 0x06000604, |
| 40 | .odtmap = 0x00000001, |
| 41 | .rfshtmg = 0x00400046, |
| 42 | .dramtmg0 = 0x09081109, |
| 43 | .addrmap0 = 0x0000001f, |
| 44 | .addrmap1 = 0x00080808, |
| 45 | .addrmap4 = 0x00000f0f, |
| 46 | .addrmap5 = 0x07070707, |
| 47 | .addrmap6 = 0x0f0f0707, |
| 48 | }; |
| 49 | |
| 50 | static struct ddrc_mp ddrc_mp_val = { |
| 51 | .pctrl_0 = 0x00000001, |
| 52 | }; |
| 53 | |
| 54 | static struct ddr_phy ddr_phy_regs_val = { |
| 55 | .phy_con0 = 0x17420f40, |
| 56 | .phy_con1 = 0x10210100, |
| 57 | .phy_con4 = 0x00060807, |
| 58 | .mdll_con0 = 0x1010007e, |
| 59 | .drvds_con0 = 0x00000d6e, |
| 60 | .cmd_sdll_con0 = 0x00000010, |
| 61 | .offset_lp_con0 = 0x0000000f, |
| 62 | .offset_rd_con0 = 0x08080808, |
| 63 | .offset_wr_con0 = 0x08080808, |
| 64 | }; |
| 65 | |
| 66 | static struct mx7_calibration calib_param = { |
| 67 | .num_val = 5, |
| 68 | .values = { |
| 69 | 0x0E407304, |
| 70 | 0x0E447304, |
| 71 | 0x0E447306, |
| 72 | 0x0E447304, |
| 73 | 0x0E447304, |
| 74 | }, |
| 75 | }; |
| 76 | |
| 77 | static void gpr_init(void) |
| 78 | { |
| 79 | struct iomuxc_gpr_base_regs *gpr_regs = |
| 80 | (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; |
| 81 | writel(0x4F400005, &gpr_regs->gpr[1]); |
| 82 | } |
| 83 | |
| 84 | static bool is_1g(void) |
| 85 | { |
| 86 | gpio_direction_input(IMX_GPIO_NR(1, 12)); |
| 87 | return !gpio_get_value(IMX_GPIO_NR(1, 12)); |
| 88 | } |
| 89 | |
| 90 | static void ddr_init(void) |
| 91 | { |
| 92 | if (is_1g()) { |
| 93 | ddrc_regs_val.addrmap5 = 0x07070707; |
| 94 | ddrc_regs_val.addrmap6 = 0x0f070707; |
| 95 | } |
| 96 | |
| 97 | mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val, |
| 98 | &calib_param); |
| 99 | } |
| 100 | |
| 101 | void board_init_f(ulong dummy) |
| 102 | { |
| 103 | arch_cpu_init(); |
| 104 | gpr_init(); |
| 105 | board_early_init_f(); |
| 106 | timer_init(); |
| 107 | preloader_console_init(); |
| 108 | ddr_init(); |
| 109 | memset(__bss_start, 0, __bss_end - __bss_start); |
| 110 | board_init_r(NULL, 0); |
| 111 | } |
| 112 | |
| 113 | void reset_cpu(ulong addr) |
| 114 | { |
| 115 | } |
| 116 | #endif |