blob: 6ead1d06309af46aadbf08906d0b643e4b423bcf [file] [log] [blame]
wdenk384cc682005-04-03 22:35:21 +00001 /*
2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003, Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27
28#include <common.h>
29#include <pci.h>
30#include <asm/processor.h>
31#include <asm/immap_85xx.h>
32#include <spd.h>
33
34#if defined(CONFIG_DDR_ECC)
35extern void ddr_enable_ecc(unsigned int dram_size);
36#endif
37
38extern long int spd_sdram(void);
39
40void local_bus_init(void);
41void sdram_init(void);
42long int fixed_sdram(void);
43
44
45int board_early_init_f (void)
46{
47#if defined(CONFIG_PCI)
48 volatile immap_t *immr = (immap_t *)CFG_IMMR;
49 volatile ccsr_pcix_t *pci = &immr->im_pcix;
50
51 pci->peer &= 0xffffffdf; /* disable master abort */
52#endif
53
54 return 0;
55}
56
57int checkboard (void)
58{
59 puts("Board: MicroSys PM854\n");
60
61#ifdef CONFIG_PCI
62 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
63 CONFIG_SYS_CLK_FREQ / 1000000);
64#else
65 printf(" PCI1: disabled\n");
66#endif
67
68 /*
69 * Initialize local bus.
70 */
71 local_bus_init();
72
73 return 0;
74}
75
76
77long int
78initdram(int board_type)
79{
80 long dram_size = 0;
81 extern long spd_sdram (void);
82 volatile immap_t *immap = (immap_t *)CFG_IMMR;
83
84 puts("Initializing\n");
85
86#if defined(CONFIG_DDR_DLL)
87 {
88 volatile ccsr_gur_t *gur= &immap->im_gur;
89 int i,x;
wdenk8b0bfc62005-04-03 23:11:38 +000090
wdenk384cc682005-04-03 22:35:21 +000091 x = 10;
wdenk8b0bfc62005-04-03 23:11:38 +000092
wdenk384cc682005-04-03 22:35:21 +000093 /*
94 * Work around to stabilize DDR DLL
95 */
96 gur->ddrdllcr = 0x81000000;
97 asm("sync;isync;msync");
98 udelay (200);
99 while (gur->ddrdllcr != 0x81000100)
100 {
101 gur->devdisr = gur->devdisr | 0x00010000;
102 asm("sync;isync;msync");
103 for (i=0; i<x; i++)
104 ;
105 gur->devdisr = gur->devdisr & 0xfff7ffff;
106 asm("sync;isync;msync");
107 x++;
108 }
wdenk8b0bfc62005-04-03 23:11:38 +0000109 }
wdenk384cc682005-04-03 22:35:21 +0000110#endif
111
112#if defined(CONFIG_SPD_EEPROM)
113 dram_size = spd_sdram ();
114#else
115 dram_size = fixed_sdram ();
116#endif
117
118#if defined(CONFIG_DDR_ECC)
119 /*
120 * Initialize and enable DDR ECC.
121 */
122 ddr_enable_ecc(dram_size);
123#endif
124 puts(" DDR: ");
125 return dram_size;
126}
127
128
129/*
130 * Initialize Local Bus
131 */
132
133void
134local_bus_init(void)
135{
136 volatile immap_t *immap = (immap_t *)CFG_IMMR;
137 volatile ccsr_gur_t *gur = &immap->im_gur;
138 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
139
140 uint clkdiv;
141 uint lbc_hz;
142 sys_info_t sysinfo;
143
144 /*
145 * Errata LBC11.
146 * Fix Local Bus clock glitch when DLL is enabled.
147 *
148 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
149 * If localbus freq is > 133Mhz, DLL can be safely enabled.
150 * Between 66 and 133, the DLL is enabled with an override workaround.
151 */
152
153 get_sys_info(&sysinfo);
154 clkdiv = lbc->lcrr & 0x0f;
155 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
156
157 if (lbc_hz < 66) {
158 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
159
160 } else if (lbc_hz >= 133) {
161 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
162
163 } else {
164 /*
165 * On REV1 boards, need to change CLKDIV before enable DLL.
166 * Default CLKDIV is 8, change it to 4 temporarily.
167 */
168 uint pvr = get_pvr();
169 uint temp_lbcdll = 0;
170
171 if (pvr == PVR_85xx_REV1) {
172 /* FIXME: Justify the high bit here. */
173 lbc->lcrr = 0x10000004;
174 }
175
176 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
177 udelay(200);
178
179 /*
180 * Sample LBC DLL ctrl reg, upshift it to set the
181 * override bits.
182 */
183 temp_lbcdll = gur->lbcdllcr;
184 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
185 asm("sync;isync;msync");
186 }
187}
188
189
190#if defined(CFG_DRAM_TEST)
191int testdram (void)
192{
193 uint *pstart = (uint *) CFG_MEMTEST_START;
194 uint *pend = (uint *) CFG_MEMTEST_END;
195 uint *p;
196
197 printf("SDRAM test phase 1:\n");
198 for (p = pstart; p < pend; p++)
199 *p = 0xaaaaaaaa;
200
201 for (p = pstart; p < pend; p++) {
202 if (*p != 0xaaaaaaaa) {
203 printf ("SDRAM test fails at: %08x\n", (uint) p);
204 return 1;
205 }
206 }
207
208 printf("SDRAM test phase 2:\n");
209 for (p = pstart; p < pend; p++)
210 *p = 0x55555555;
211
212 for (p = pstart; p < pend; p++) {
213 if (*p != 0x55555555) {
214 printf ("SDRAM test fails at: %08x\n", (uint) p);
215 return 1;
216 }
217 }
218
219 printf("SDRAM test passed.\n");
220 return 0;
221}
222#endif
223
224
225#if !defined(CONFIG_SPD_EEPROM)
226/*************************************************************************
227 * fixed sdram init -- doesn't use serial presence detect.
228 ************************************************************************/
229long int fixed_sdram (void)
230{
231 #ifndef CFG_RAMBOOT
232 volatile immap_t *immap = (immap_t *)CFG_IMMR;
233 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
234
235 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
236 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
237 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
238 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
239 ddr->sdram_mode = CFG_DDR_MODE;
240 ddr->sdram_interval = CFG_DDR_INTERVAL;
241 #if defined (CONFIG_DDR_ECC)
242 ddr->err_disable = 0x0000000D;
243 ddr->err_sbe = 0x00ff0000;
244 #endif
245 asm("sync;isync;msync");
246 udelay(500);
247 #if defined (CONFIG_DDR_ECC)
248 /* Enable ECC checking */
249 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
250 #else
251 ddr->sdram_cfg = CFG_DDR_CONTROL;
252 #endif
253 asm("sync; isync; msync");
254 udelay(500);
255 #endif
256 return CFG_SDRAM_SIZE * 1024 * 1024;
257}
258#endif /* !defined(CONFIG_SPD_EEPROM) */
259
260
261#if defined(CONFIG_PCI)
262/*
263 * Initialize PCI Devices, report devices found.
264 */
265
266#ifndef CONFIG_PCI_PNP
267static struct pci_config_table pci_pm854_config_table[] = {
268 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
269 PCI_IDSEL_NUMBER, PCI_ANY_ID,
270 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
271 PCI_ENET0_MEMADDR,
272 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
273 } },
274 { }
275};
276#endif
277
278
279static struct pci_controller hose = {
280#ifndef CONFIG_PCI_PNP
281 config_table: pci_pm854_config_table,
282#endif
283};
284
285#endif /* CONFIG_PCI */
286
287
288void
289pci_init_board(void)
290{
291#ifdef CONFIG_PCI
wdenk384cc682005-04-03 22:35:21 +0000292 pci_mpc85xx_init(&hose);
293#endif /* CONFIG_PCI */
294}